brentkung_32.vhd

32 bit brentkung adder tree

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity brentkung_32 is
    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
           b : in  STD_LOGIC_VECTOR (31 downto 0);
			  ci : in  STD_LOGIC;
			  co : out  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (31 downto 0));
end brentkung_32;

architecture Behavioral of brentkung_32 is
    
    
    -- define the FA
	component fulladder 
	port (In1, In2, c_in: in std_logic;
         sum, c_out : out std_logic ; p,g : out std_logic);
	end component;
    
	-- define the HA
	component halfadder 
	port (a, b: in std_logic;sum, carry: out std_logic);
	end component;
	
	
	
	-- define the XOR
	component xor_2 
	GENERIC ( delay : TIME := 2 NS); 
   PORT (in_1, in_2 : IN STD_LOGIC; out_1 : OUT STD_LOGIC); 
	end component;
	-- define cell
	component cell 
	Port ( gn : in STD_LOGIC;pn : in  STD_LOGIC;
           gb : in  STD_LOGIC; pb : in  STD_LOGIC;
           go : out  STD_LOGIC; po : out  STD_LOGIC);
	end component;

signal gs0, gs1, gs2,
			gs3, gs4, gs5,
			gs6, gs7, gs8 : STD_LOGIC_VECTOR (31 downto 0); 
signal ps0, ps1, ps2,
			ps3, ps4, ps5,
			ps6, ps7, ps8 : STD_LOGIC_VECTOR (31 downto 0); 

begin

	-- pre-proccessing
	oGen_0 : for i in 0 to 31 generate
		if_1 : if (i > 0) generate
			oHA : halfadder port map (a(i), b(i),pS0(i), gS0(i) );
		end generate;
		if_2 : if (i = 0) generate
			oFA : fulladder port map (a(0), b(0), ci, open, open,pS0(0),gS0(0));
		end generate;
	end generate;
	
	-- level 1
	oGen_1 : for i in 0 to 31 generate
		if_1 : if i mod 2 = 0 generate
			gs1(i) <= gs0(i); ps1(i) <= ps0(i);
		end generate;
		if_2 : if i mod 2 = 1 generate
			ocell : cell port map (gs0(i), ps0(i),gs0(i-1), ps0(i-1), gs1(i), ps1(i));
		end generate;
	end generate;
	
	-- level 2
	oGen_2 : for i in 0 to 31 generate
		if_1 : if not(i mod 4 = 3) generate
			gs2(i) <= gs1(i); ps2(i) <= ps1(i);
		end generate;
		if_2 : if i mod 4 = 3 generate
			ocell : cell port map (gs1(i), ps1(i),
				gs1(i-(i mod 4)+1), ps1(i-(i mod 4)+1), 
				gs2(i), ps2(i));
		end generate;
	end generate;
	
	-- level 3
	oGen_3 : for i in 0 to 31 generate
		if_1 : if not(i mod 8 = 7) generate
			gs3(i) <= gs2(i); ps3(i) <= ps2(i);
		end generate;
		if_2 : if i mod 8 = 7 generate
			ocell : cell port map (gs2(i), ps2(i),	gs2(i-(i mod 8)+3), ps2(i-(i mod 8)+3), 
				gs3(i), ps3(i));
		end generate;
	end generate;
	
	-- level 4
	oGen_4 : for i in 0 to 31 generate
	 if_1 : if not(i mod 16 = 15) generate
			gs4(i) <= gs3(i); ps4(i) <= ps3(i);
		end generate;
		if_2 : if i mod 16 = 15 generate
			ocell : cell port map (gs3(i), ps3(i),
				gs3(i-(i mod 16)+7), ps3(i-(i mod 16)+7), 
				gs4(i), ps4(i));
		end generate;
	end generate;	

	-- level 5
	oGen_5 : for i in 0 to 31 generate
		if_1 : if not(i = 31) and not(i = 23) generate
			gs5(i) <= gs4(i); ps5(i) <= ps4(i);
		end generate;
		if_2 : if i = 31 or i = 23 generate
			ocell : cell port map (gs4(i), ps4(i),
				gs4(15), ps4(15), gs5(i), ps5(i));
		end generate;
	end generate;	

	-- level 6
	oGen_6 : for i in 0 to 31 generate
		if_1 : if not(i mod 4 = 3) or (i < 8) generate
			gs6(i) <= gs5(i); ps6(i) <= ps5(i);
		end generate;
		if_2 : if (i mod 4 = 3) and (i > 7) generate
			ocell : cell port map (gs5(i), ps5(i),
				gs5(i-(i mod 8)-1), ps5(i-(i mod 8)-1), 
				gs6(i), ps6(i));
		end generate;
	end generate;	


	-- level 7
	oGen_7 : for i in 0 to 31 generate
		if_1 : if not(i mod 4 = 1) or (i < 4) generate
			gs7(i) <= gs6(i); ps7(i) <= ps6(i);
		end generate;
		if_2 : if (i mod 4 = 1) and (i > 3) generate
			ocell : cell port map (gs6(i), ps6(i),
				gs6(i-2), ps6(i-2), gs7(i), ps7(i));
		end generate;
	end generate;	

	-- level 8
	oGen_8 : for i in 0 to 31 generate
		if_1 : if not(i mod 2 = 0) or (i < 2) generate
			gs8(i) <= gs7(i); ps8(i) <= ps7(i);
		end generate;
		if_2 : if (i mod 2 = 0) and (i > 1) generate
			ocell : cell port map (gs7(i), ps7(i),
				gs7(i-1), ps7(i-1), gs8(i), ps8(i));
		end generate;
	end generate;	
	
	-- post-proccessing
	xOring : xor_2 port map (ci, ps0(0), s(0));
	Gen_9 : for i in 1 to 31 generate
		xoring : xor_2 port map (gs8(i-1), ps0(i), s(i));
	end generate;
	co <= gs8(31);
	
end Behavioral;