cnt5.vhd

使用VHDL语言实现计数器功能 ……使用VHDL语言实现计数器功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt5 is
port (clk,ck:in std_logic;
      sel:in std_logic_vector(2 downto 0);
      y:buffer std_logic_vector(3 downto 0);
     duan:out std_logic_vector(5 downto 0);
     sm:out std_logic_vector(6 downto 0));
end cnt5;
architecture a of cnt5 is
type state_type is(s0,s1,s2,s3,s4);
 signal state :state_type;
 signal tmp:integer range 0 to 5;
 signal q_s:std_logic_vector(3 downto 0);

 begin
state_p:process(clk)
  begin 
   if clk'event and clk='1' then
   case state is 
   when s0=>state<=s1;
   when s1=>state<=s2;
   when s2=>state<=s3;
   when s3=>state<=s4;
   when s4=>state<=s0;
   end case;
   end if ;
end process;




out_p:process(state)
begin
  case state is 
  when s0=>if sel="000" then y<="0000";
           elsif sel="001" then y<="0000";
           elsif sel="010" then y<="0001";
           elsif sel="011" then y<="0101";
           elsif sel="100" then y<="0000";
           elsif sel="101" then y<="0101";
           elsif sel="110" then y<="0010";
           else y<="1001";
          end if;
 when s1=>if sel="000" then y<="0001";
           elsif sel="001" then y<="0010";
           elsif sel="010" then y<="0011";
           elsif sel="011" then y<="0100";
           elsif sel="100" then y<="0001";
           elsif sel="101" then y<="0110";
           elsif sel="110" then y<="0100";
           else y<="1000";
          end if;
when s2=>if sel="000" then y<="0010";
           elsif sel="001" then y<="0100";
           elsif sel="010" then y<="0101";
           elsif sel="011" then y<="0011";
           elsif sel="100" then y<="0011";
           elsif sel="101" then y<="0111";
           elsif sel="110" then y<="0110";
           else y<="0111";
          end if;
when s3=>if sel="000" then y<="0011";
           elsif sel="001" then y<="0110";
           elsif sel="010" then y<="0111";
           elsif sel="011" then y<="0010";
           elsif sel="100" then y<="0110";
           elsif sel="101" then y<="1000";
           elsif sel="110" then y<="1000";
           else y<="0110";
          end if;
when s4=>if sel="000" then y<="0100";
           elsif sel="001" then y<="1000";
           elsif sel="010" then y<="1001";
           elsif sel="011" then y<="0001";
           elsif sel="100" then y<="1001";
           elsif sel="101" then y<="1001";
           elsif sel="110" then y<="0000";
           else y<="0101";
          end if;
end case;
end process;


process(ck)
begin
if ck'event and ck='1' then
if tmp=0 then q_s<=y;duan<="000001";
elsif tmp=1 then q_s<=y;duan<="000010";
elsif tmp=2 then q_s<=y;duan<="000100";
elsif tmp=3 then q_s<="000"&sel(2);duan<="001000";
elsif tmp=4 then q_s<="000"&sel(1);duan<="010000";
else q_s<="000"&sel(0);duan<="100000";
end if;
if tmp=5 then tmp<=0;else tmp<=tmp+1;end if;
end if;
end process;



process(q_s)
begin
case q_s is
when "0000"=>sm<="1111110";
when "0001"=>sm<="0110000";
when "0010"=>sm<="1101101";
when "0011"=>sm<="1111001";
when "0100"=>sm<="0110011";
when "0101"=>sm<="1011011";
when "0110"=>sm<="1011111";
when "0111"=>sm<="1110000";
when "1000"=>sm<="1111111";
when "1001"=>sm<="1111011";
when others=>sm<="0000000";
end case;
end process;
end;