cslr_mibspi.h

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/** =========================================================
*   Copyright (c) Texas Instruments Inc 2002, 2003
*
*   Use of this software is controlled by the terms and conditions found
*   in the license agreement under which this software has been supplied
*   priovided
*   ==========================================================
*/

#ifndef _CSLR_MIBSPI_001_H_
#define _CSLR_MIBSPI_001_H_

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 SPIGCR0;
    volatile Uint32 SPIGCR1;
    volatile Uint32 SPIINT0;
    volatile Uint32 SPILVL;
    volatile Uint32 SPIFLG;
    volatile Uint32 SPIPC0;
    volatile Uint32 SPIPC1;
    volatile Uint32 SPIPC2;
    volatile Uint32 SPIPC3;
    volatile Uint32 SPIPC4;
    volatile Uint32 SPIPC5;
    volatile Uint32 SPIPC6;
    volatile Uint32 SPIPC7;
    volatile Uint32 SPIPC8;
    volatile Uint32 SPIDAT0;
    volatile Uint32 SPIDAT1;
    volatile Uint32 SPIBUF;
    volatile Uint32 SPIEMU;
    volatile Uint32 SPIDELAY;
    volatile Uint32 SPIDEF;
    volatile Uint32 SPIFMT[4];
    volatile Uint32 TGINTVEC[2];
    const char RSVD0[8];
    volatile Uint32 MIBSPIE;
    volatile Uint32 TGITENST;
    volatile Uint32 TGITENCR;
    volatile Uint32 TGITLVST;
    volatile Uint32 TGITLVCR;
    volatile Uint32 TGINTFLAG;
    const char RSVD1[8];
    volatile Uint32 TICKCNT;
    volatile Uint32 LTGPEND;
    volatile Uint32 TGCTRL[16];
    volatile Uint32 DMACTRL[8];
    volatile Uint32 DMACOUNT[8];
    volatile Uint32 DMACNTLEN;
    const char RSVD2[740];
    volatile Uint32 TXBUF[128];
    volatile Uint32 RXBUF[128];
} CSL_MibspiRegs;

/**************************************************************************\
* Register Id's
\**************************************************************************/
typedef enum  {
   CSL_MIBSPI_SPIGCR0 = 0x0000u,
   CSL_MIBSPI_SPIGCR1 = 0x0004u,
   CSL_MIBSPI_SPIINT0 = 0x0008u,
   CSL_MIBSPI_SPILVL = 0x000cu,
   CSL_MIBSPI_SPIFLG = 0x0010u,
   CSL_MIBSPI_SPIPC0 = 0x0014u,
   CSL_MIBSPI_SPIPC1 = 0x0018u,
   CSL_MIBSPI_SPIPC2 = 0x001cu,
   CSL_MIBSPI_SPIPC3 = 0x0020u,
   CSL_MIBSPI_SPIPC4 = 0x0024u,
   CSL_MIBSPI_SPIPC5 = 0x0028u,
   CSL_MIBSPI_SPIPC6 = 0x002cu,
   CSL_MIBSPI_SPIPC7 = 0x0030u,
   CSL_MIBSPI_SPIPC8 = 0x0034u,
   CSL_MIBSPI_SPIDAT0 = 0x0038u,
   CSL_MIBSPI_SPIDAT1 = 0x003cu,
   CSL_MIBSPI_SPIBUF = 0x0040u,
   CSL_MIBSPI_SPIEMU = 0x0044u,
   CSL_MIBSPI_SPIDELAY = 0x0048u,
   CSL_MIBSPI_SPIDEF = 0x004cu,
   CSL_MIBSPI_SPIFMT = 0x0050u,
   CSL_MIBSPI_TGINTVEC = 0x0060u,
   CSL_MIBSPI_MIBSPIE = 0x0070u,
   CSL_MIBSPI_TGITENST = 0x0074u,
   CSL_MIBSPI_TGITENCR = 0x0078u,
   CSL_MIBSPI_TGITLVST = 0x007cu,
   CSL_MIBSPI_TGITLVCR = 0x0080u,
   CSL_MIBSPI_TGINTFLAG = 0x0084u,
   CSL_MIBSPI_TICKCNT = 0x0090u,
   CSL_MIBSPI_LTGPEND = 0x0094u,
   CSL_MIBSPI_TGCTRL = 0x0098u,
   CSL_MIBSPI_DMACTRL = 0x00d8u,
   CSL_MIBSPI_DMACOUNT = 0x00f8u,
   CSL_MIBSPI_DMACNTLEN = 0x0118u,
   CSL_MIBSPI_TXBUF = 0x0400u,
   CSL_MIBSPI_RXBUF = 0x0500u
} CSL_MibspiRegIds;

/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_MibspiRegs  * CSL_MibspiRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* SPIGCR0 */

#define CSL_MIBSPI_SPIGCR0_RESET_MASK    (0x00000001u)
#define CSL_MIBSPI_SPIGCR0_RESET_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIGCR0_RESET_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR0_RESET_YES     (0x00000000u)
#define CSL_MIBSPI_SPIGCR0_RESET_NO      (0x00000001u)

#define CSL_MIBSPI_SPIGCR0_RESETVAL      (0x00000000u)

/* SPIGCR1 */

#define CSL_MIBSPI_SPIGCR1_SPIEN_MASK    (0x01000000u)
#define CSL_MIBSPI_SPIGCR1_SPIEN_SHIFT   (0x00000018u)
#define CSL_MIBSPI_SPIGCR1_SPIEN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_SPIEN_INRESET (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_SPIEN_ACTIVE  (0x00000001u)

#define CSL_MIBSPI_SPIGCR1_LOOPBK_MASK   (0x00010000u)
#define CSL_MIBSPI_SPIGCR1_LOOPBK_SHIFT  (0x00000010u)
#define CSL_MIBSPI_SPIGCR1_LOOPBK_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_LOOPBK_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_LOOPBK_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIGCR1_PWRDN_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIGCR1_PWRDN_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIGCR1_PWRDN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_PWRDN_ACTIVE  (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_PWRDN_PWRDN   (0x00000001u)

#define CSL_MIBSPI_SPIGCR1_CLKMOD_MASK   (0x00000002u)
#define CSL_MIBSPI_SPIGCR1_CLKMOD_SHIFT  (0x00000001u)
#define CSL_MIBSPI_SPIGCR1_CLKMOD_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_CLKMOD_EXTERNAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_CLKMOD_INTERNAL (0x00000001u)

#define CSL_MIBSPI_SPIGCR1_MASTER_MASK   (0x00000001u)
#define CSL_MIBSPI_SPIGCR1_MASTER_SHIFT  (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_MASTER_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_MASTER_NO     (0x00000000u)
#define CSL_MIBSPI_SPIGCR1_MASTER_YES    (0x00000001u)

#define CSL_MIBSPI_SPIGCR1_RESETVAL      (0x00000000u)

/* SPIINT0 */

#define CSL_MIBSPI_SPIINT0_ENAHIGHZ_MASK (0x01000000u)
#define CSL_MIBSPI_SPIINT0_ENAHIGHZ_SHIFT (0x00000018u)
#define CSL_MIBSPI_SPIINT0_ENAHIGHZ_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_ENAHIGHZ_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_ENAHIGHZ_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_DMAREQ_MASK   (0x00010000u)
#define CSL_MIBSPI_SPIINT0_DMAREQ_SHIFT  (0x00000010u)
#define CSL_MIBSPI_SPIINT0_DMAREQ_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_DMAREQ_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_DMAREQ_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_RXINT_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIINT0_RXINT_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIINT0_RXINT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_RXINT_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_RXINT_ENABLE  (0x00000001u)

#define CSL_MIBSPI_SPIINT0_OVRNINT_MASK  (0x00000040u)
#define CSL_MIBSPI_SPIINT0_OVRNINT_SHIFT (0x00000006u)
#define CSL_MIBSPI_SPIINT0_OVRNINT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_OVRNINT_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_OVRNINT_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_BITERR_MASK   (0x00000010u)
#define CSL_MIBSPI_SPIINT0_BITERR_SHIFT  (0x00000004u)
#define CSL_MIBSPI_SPIINT0_BITERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_BITERR_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_BITERR_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_DESYNC_MASK   (0x00000008u)
#define CSL_MIBSPI_SPIINT0_DESYNC_SHIFT  (0x00000003u)
#define CSL_MIBSPI_SPIINT0_DESYNC_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_DESYNC_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_DESYNC_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_PARERR_MASK   (0x00000004u)
#define CSL_MIBSPI_SPIINT0_PARERR_SHIFT  (0x00000002u)
#define CSL_MIBSPI_SPIINT0_PARERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_PARERR_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_PARERR_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_TIMEOUT_MASK  (0x00000002u)
#define CSL_MIBSPI_SPIINT0_TIMEOUT_SHIFT (0x00000001u)
#define CSL_MIBSPI_SPIINT0_TIMEOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIINT0_TIMEOUT_DISABLE (0x00000000u)
#define CSL_MIBSPI_SPIINT0_TIMEOUT_ENABLE (0x00000001u)

#define CSL_MIBSPI_SPIINT0_RESETVAL      (0x00000000u)

/* SPILVL */

#define CSL_MIBSPI_SPILVL_RXINT_MASK     (0x00000100u)
#define CSL_MIBSPI_SPILVL_RXINT_SHIFT    (0x00000008u)
#define CSL_MIBSPI_SPILVL_RXINT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_RXINT_INT0     (0x00000000u)
#define CSL_MIBSPI_SPILVL_RXINT_INT1     (0x00000001u)

#define CSL_MIBSPI_SPILVL_OVRNINT_MASK   (0x00000040u)
#define CSL_MIBSPI_SPILVL_OVRNINT_SHIFT  (0x00000006u)
#define CSL_MIBSPI_SPILVL_OVRNINT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_OVRNINT_INT0   (0x00000000u)
#define CSL_MIBSPI_SPILVL_OVRNINT_INT1   (0x00000001u)

#define CSL_MIBSPI_SPILVL_BITERR_MASK    (0x00000010u)
#define CSL_MIBSPI_SPILVL_BITERR_SHIFT   (0x00000004u)
#define CSL_MIBSPI_SPILVL_BITERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_BITERR_INT0    (0x00000000u)
#define CSL_MIBSPI_SPILVL_BITERR_INT1    (0x00000001u)

#define CSL_MIBSPI_SPILVL_DESYNC_MASK    (0x00000008u)
#define CSL_MIBSPI_SPILVL_DESYNC_SHIFT   (0x00000003u)
#define CSL_MIBSPI_SPILVL_DESYNC_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_DESYNC_INT0    (0x00000000u)
#define CSL_MIBSPI_SPILVL_DESYNC_INT1    (0x00000001u)

#define CSL_MIBSPI_SPILVL_PARERR_MASK    (0x00000004u)
#define CSL_MIBSPI_SPILVL_PARERR_SHIFT   (0x00000002u)
#define CSL_MIBSPI_SPILVL_PARERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_PARERR_INT0    (0x00000000u)
#define CSL_MIBSPI_SPILVL_PARERR_INT1    (0x00000001u)

#define CSL_MIBSPI_SPILVL_TIMEOUT_MASK   (0x00000002u)
#define CSL_MIBSPI_SPILVL_TIMEOUT_SHIFT  (0x00000001u)
#define CSL_MIBSPI_SPILVL_TIMEOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPILVL_TIMEOUT_INT0   (0x00000000u)
#define CSL_MIBSPI_SPILVL_TIMEOUT_INT1   (0x00000001u)

#define CSL_MIBSPI_SPILVL_RESETVAL       (0x00000000u)

/* SPIFLG */

#define CSL_MIBSPI_SPIFLG_RXINTFLAG_MASK (0x00000100u)
#define CSL_MIBSPI_SPIFLG_RXINTFLAG_SHIFT (0x00000008u)
#define CSL_MIBSPI_SPIFLG_RXINTFLAG_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_RXINTFLAG_NO   (0x00000000u)
#define CSL_MIBSPI_SPIFLG_RXINTFLAG_YES  (0x00000001u)

#define CSL_MIBSPI_SPIFLG_RCVROVRN_MASK  (0x00000040u)
#define CSL_MIBSPI_SPIFLG_RCVROVRN_SHIFT (0x00000006u)
#define CSL_MIBSPI_SPIFLG_RCVROVRN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_RCVROVRN_NO    (0x00000000u)
#define CSL_MIBSPI_SPIFLG_RCVROVRN_YES   (0x00000001u)

#define CSL_MIBSPI_SPIFLG_BITERROR_MASK  (0x00000010u)
#define CSL_MIBSPI_SPIFLG_BITERROR_SHIFT (0x00000004u)
#define CSL_MIBSPI_SPIFLG_BITERROR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_BITERROR_NO    (0x00000000u)
#define CSL_MIBSPI_SPIFLG_BITERROR_YES   (0x00000001u)

#define CSL_MIBSPI_SPIFLG_DESYNC_MASK    (0x00000008u)
#define CSL_MIBSPI_SPIFLG_DESYNC_SHIFT   (0x00000003u)
#define CSL_MIBSPI_SPIFLG_DESYNC_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_DESYNC_NO      (0x00000000u)
#define CSL_MIBSPI_SPIFLG_DESYNC_YES     (0x00000001u)

#define CSL_MIBSPI_SPIFLG_PARITYERR_MASK (0x00000004u)
#define CSL_MIBSPI_SPIFLG_PARITYERR_SHIFT (0x00000002u)
#define CSL_MIBSPI_SPIFLG_PARITYERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_PARITYERR_NO   (0x00000000u)
#define CSL_MIBSPI_SPIFLG_PARITYERR_YES  (0x00000001u)

#define CSL_MIBSPI_SPIFLG_TIMEOUT_MASK   (0x00000002u)
#define CSL_MIBSPI_SPIFLG_TIMEOUT_SHIFT  (0x00000001u)
#define CSL_MIBSPI_SPIFLG_TIMEOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIFLG_TIMEOUT_NO     (0x00000000u)
#define CSL_MIBSPI_SPIFLG_TIMEOUT_YES    (0x00000001u)

#define CSL_MIBSPI_SPIFLG_RESETVAL       (0x00000000u)

/* SPIPC0 */

#define CSL_MIBSPI_SPIPC0_SOMIFUN_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC0_SOMIFUN_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC0_SOMIFUN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC0_SOMIFUN_GPIO   (0x00000000u)
#define CSL_MIBSPI_SPIPC0_SOMIFUN_SPI    (0x00000001u)

#define CSL_MIBSPI_SPIPC0_SIMOFUN_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC0_SIMOFUN_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC0_SIMOFUN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC0_SIMOFUN_GPIO   (0x00000000u)
#define CSL_MIBSPI_SPIPC0_SIMOFUN_SPI    (0x00000001u)

#define CSL_MIBSPI_SPIPC0_CLKFUN_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC0_CLKFUN_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC0_CLKFUN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC0_CLKFUN_GPIO    (0x00000000u)
#define CSL_MIBSPI_SPIPC0_CLKFUN_SPI     (0x00000001u)

#define CSL_MIBSPI_SPIPC0_ENAFUN_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC0_ENAFUN_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC0_ENAFUN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC0_ENAFUN_GPIO    (0x00000000u)
#define CSL_MIBSPI_SPIPC0_ENAFUN_SPI     (0x00000001u)

#define CSL_MIBSPI_SPIPC0_SCSFUN_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC0_SCSFUN_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC0_SCSFUN_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIPC0_RESETVAL       (0x00000000u)

/* SPIPC1 */

#define CSL_MIBSPI_SPIPC1_SOMIDIR_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC1_SOMIDIR_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC1_SOMIDIR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC1_SOMIDIR_IN     (0x00000000u)
#define CSL_MIBSPI_SPIPC1_SOMIDIR_OUT    (0x00000001u)

#define CSL_MIBSPI_SPIPC1_SIMODIR_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC1_SIMODIR_SHIFT  (0x0000000Au)
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