cslr_mibspi.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 1,313 行 · 第 1/4 页

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#define CSL_MIBSPI_SPIPC1_SIMODIR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC1_SIMODIR_IN     (0x00000000u)
#define CSL_MIBSPI_SPIPC1_SIMODIR_OUT    (0x00000001u)

#define CSL_MIBSPI_SPIPC1_CLKDIR_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC1_CLKDIR_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC1_CLKDIR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC1_CLKDIR_IN      (0x00000000u)
#define CSL_MIBSPI_SPIPC1_CLKDIR_OUT     (0x00000001u)

#define CSL_MIBSPI_SPIPC1_ENADIR_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC1_ENADIR_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC1_ENADIR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC1_ENADIR_IN      (0x00000000u)
#define CSL_MIBSPI_SPIPC1_ENADIR_OUT     (0x00000001u)

#define CSL_MIBSPI_SPIPC1_SCSDIR_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC1_SCSDIR_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC1_SCSDIR_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIPC1_RESETVAL       (0x00000000u)

/* SPIPC2 */

#define CSL_MIBSPI_SPIPC2_SOMI_MASK      (0x00000800u)
#define CSL_MIBSPI_SPIPC2_SOMI_SHIFT     (0x0000000Bu)
#define CSL_MIBSPI_SPIPC2_SOMI_RESETVAL  (0x00000000u)
#define CSL_MIBSPI_SPIPC2_SOMI_LO        (0x00000000u)
#define CSL_MIBSPI_SPIPC2_SOMI_HI        (0x00000001u)

#define CSL_MIBSPI_SPIPC2_SIMODIN_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC2_SIMODIN_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC2_SIMODIN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC2_SIMODIN_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC2_SIMODIN_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC2_CLKDIN_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC2_CLKDIN_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC2_CLKDIN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC2_CLKDIN_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC2_CLKDIN_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC2_ENADIN_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC2_ENADIN_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC2_ENADIN_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC2_ENADIN_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC2_ENADIN_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC2_SCSDIN_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC2_SCSDIN_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC2_SCSDIN_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIPC2_RESETVAL       (0x00000000u)

/* SPIPC3 */

#define CSL_MIBSPI_SPIPC3_SOMIDOUT_MASK  (0x00000800u)
#define CSL_MIBSPI_SPIPC3_SOMIDOUT_SHIFT (0x0000000Bu)
#define CSL_MIBSPI_SPIPC3_SOMIDOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC3_SOMIDOUT_LO    (0x00000000u)
#define CSL_MIBSPI_SPIPC3_SOMIDOUT_HI    (0x00000001u)

#define CSL_MIBSPI_SPIPC3_SIMODOUT_MASK  (0x00000400u)
#define CSL_MIBSPI_SPIPC3_SIMODOUT_SHIFT (0x0000000Au)
#define CSL_MIBSPI_SPIPC3_SIMODOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC3_SIMODOUT_LO    (0x00000000u)
#define CSL_MIBSPI_SPIPC3_SIMODOUT_HI    (0x00000001u)

#define CSL_MIBSPI_SPIPC3_CLKDOUT_MASK   (0x00000200u)
#define CSL_MIBSPI_SPIPC3_CLKDOUT_SHIFT  (0x00000009u)
#define CSL_MIBSPI_SPIPC3_CLKDOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC3_CLKDOUT_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC3_CLKDOUT_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC3_ENADOUT_MASK   (0x00000100u)
#define CSL_MIBSPI_SPIPC3_ENADOUT_SHIFT  (0x00000008u)
#define CSL_MIBSPI_SPIPC3_ENADOUT_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC3_ENADOUT_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC3_ENADOUT_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC3_SCSDOUT_MASK   (0x000000FFu)
#define CSL_MIBSPI_SPIPC3_SCSDOUT_SHIFT  (0x00000000u)
#define CSL_MIBSPI_SPIPC3_SCSDOUT_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIPC3_RESETVAL       (0x00000000u)

/* SPIPC4 */

#define CSL_MIBSPI_SPIPC4_SOMISET_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC4_SOMISET_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC4_SOMISET_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC4_SOMISET_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC4_SOMISET_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC4_SIMOSET_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC4_SIMOSET_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC4_SIMOSET_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC4_SIMOSET_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC4_SIMOSET_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC4_CLKSET_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC4_CLKSET_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC4_CLKSET_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC4_CLKSET_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC4_CLKSET_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC4_ENASET_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC4_ENASET_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC4_ENASET_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC4_ENASET_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC4_ENASET_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC4_SCSSET_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC4_SCSSET_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC4_SCSSET_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIPC4_RESETVAL       (0x00000000u)

/* SPIPC5 */

#define CSL_MIBSPI_SPIPC5_SOMICLR_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC5_SOMICLR_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC5_SOMICLR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SOMICLR_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SOMICLR_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC5_SIMOCLR_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC5_SIMOCLR_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC5_SIMOCLR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SIMOCLR_LO     (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SIMOCLR_HI     (0x00000001u)

#define CSL_MIBSPI_SPIPC5_CLKCLR_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC5_CLKCLR_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC5_CLKCLR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC5_CLKCLR_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC5_CLKCLR_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC5_ENACLR_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC5_ENACLR_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC5_ENACLR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC5_ENACLR_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC5_ENACLR_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC5_SCSCLR_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC5_SCSCLR_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SCSCLR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SCSCLR_LO      (0x00000000u)
#define CSL_MIBSPI_SPIPC5_SCSCLR_HI      (0x00000001u)

#define CSL_MIBSPI_SPIPC5_RESETVAL       (0x00000000u)

/* SPIPC6 */

#define CSL_MIBSPI_SPIPC6_SOMIPDR_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC6_SOMIPDR_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC6_SOMIPDR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SOMIPDR_LOGIC1 (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SOMIPDR_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC6_SIMOPDR_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC6_SIMOPDR_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC6_SIMOPDR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SIMOPDR_LOGIC1 (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SIMOPDR_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC6_CLKPDR_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC6_CLKPDR_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC6_CLKPDR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC6_CLKPDR_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC6_CLKPDR_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC6_ENAPDR_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC6_ENAPDR_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC6_ENAPDR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC6_ENAPDR_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC6_ENAPDR_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC6_SCSPDR_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC6_SCSPDR_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SCSPDR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SCSPDR_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC6_SCSPDR_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC6_RESETVAL       (0x00000000u)

/* SPIPC7 */

#define CSL_MIBSPI_SPIPC7_SOMIIPE_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC7_SOMIIPE_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC7_SOMIIPE_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SOMIIPE_ENABLE (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SOMIIPE_DISABLE (0x00000001u)

#define CSL_MIBSPI_SPIPC7_SIMOIPE_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC7_SIMOIPE_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC7_SIMOIPE_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SIMOIPE_ENABLE (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SIMOIPE_DISABLE (0x00000001u)

#define CSL_MIBSPI_SPIPC7_CLKIPE_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC7_CLKIPE_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC7_CLKIPE_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC7_CLKIPE_ENABLE  (0x00000000u)
#define CSL_MIBSPI_SPIPC7_CLKIPE_DISABLE (0x00000001u)

#define CSL_MIBSPI_SPIPC7_ENAIPE_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC7_ENAIPE_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC7_ENAIPE_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC7_ENAIPE_ENABLE  (0x00000000u)
#define CSL_MIBSPI_SPIPC7_ENAIPE_DISABLE (0x00000001u)

#define CSL_MIBSPI_SPIPC7_SCSIPE_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC7_SCSIPE_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SCSIPE_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SCSIPE_ENABLE  (0x00000000u)
#define CSL_MIBSPI_SPIPC7_SCSIPE_DISABLE (0x00000001u)

#define CSL_MIBSPI_SPIPC7_RESETVAL       (0x00000000u)

/* SPIPC8 */

#define CSL_MIBSPI_SPIPC8_SOMIPSL_MASK   (0x00000800u)
#define CSL_MIBSPI_SPIPC8_SOMIPSL_SHIFT  (0x0000000Bu)
#define CSL_MIBSPI_SPIPC8_SOMIPSL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SOMIPSL_LOGIC1 (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SOMIPSL_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC8_SIMOPSL_MASK   (0x00000400u)
#define CSL_MIBSPI_SPIPC8_SIMOPSL_SHIFT  (0x0000000Au)
#define CSL_MIBSPI_SPIPC8_SIMOPSL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SIMOPSL_LOGIC1 (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SIMOPSL_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC8_CLKPSL_MASK    (0x00000200u)
#define CSL_MIBSPI_SPIPC8_CLKPSL_SHIFT   (0x00000009u)
#define CSL_MIBSPI_SPIPC8_CLKPSL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC8_CLKPSL_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC8_CLKPSL_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC8_ENAPSL_MASK    (0x00000100u)
#define CSL_MIBSPI_SPIPC8_ENAPSL_SHIFT   (0x00000008u)
#define CSL_MIBSPI_SPIPC8_ENAPSL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC8_ENAPSL_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC8_ENAPSL_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC8_SCSPSL_MASK    (0x000000FFu)
#define CSL_MIBSPI_SPIPC8_SCSPSL_SHIFT   (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SCSPSL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SCSPSL_LOGIC1  (0x00000000u)
#define CSL_MIBSPI_SPIPC8_SCSPSL_TRISTATE (0x00000001u)

#define CSL_MIBSPI_SPIPC8_RESETVAL       (0x00000000u)

/* SPIDAT0 */

#define CSL_MIBSPI_SPIDAT0_SPIDAT0_MASK  (0x0000FFFFu)
#define CSL_MIBSPI_SPIDAT0_SPIDAT0_SHIFT (0x00000000u)
#define CSL_MIBSPI_SPIDAT0_SPIDAT0_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIDAT0_RESETVAL      (0x00000000u)

/* SPIDAT1 */

#define CSL_MIBSPI_SPIDAT1_CSHOLD_MASK   (0x10000000u)
#define CSL_MIBSPI_SPIDAT1_CSHOLD_SHIFT  (0x0000001Cu)
#define CSL_MIBSPI_SPIDAT1_CSHOLD_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_CSHOLD_NO     (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_CSHOLD_YES    (0x00000001u)

#define CSL_MIBSPI_SPIDAT1_WDEL_MASK     (0x04000000u)
#define CSL_MIBSPI_SPIDAT1_WDEL_SHIFT    (0x0000001Au)
#define CSL_MIBSPI_SPIDAT1_WDEL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_WDEL_NODELAY  (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_WDEL_DELAY    (0x00000001u)

#define CSL_MIBSPI_SPIDAT1_DFSEL_MASK    (0x03000000u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_SHIFT   (0x00000018u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_FMT0    (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_FMT1    (0x00000001u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_FMT2    (0x00000002u)
#define CSL_MIBSPI_SPIDAT1_DFSEL_FMT3    (0x00000003u)

#define CSL_MIBSPI_SPIDAT1_CSNR_MASK     (0x00FF0000u)
#define CSL_MIBSPI_SPIDAT1_CSNR_SHIFT    (0x00000010u)
#define CSL_MIBSPI_SPIDAT1_CSNR_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIDAT1_SPIDAT1_MASK  (0x0000FFFFu)
#define CSL_MIBSPI_SPIDAT1_SPIDAT1_SHIFT (0x00000000u)
#define CSL_MIBSPI_SPIDAT1_SPIDAT1_RESETVAL (0x00000000u)

#define CSL_MIBSPI_SPIDAT1_RESETVAL      (0x00000000u)

/* SPIBUF */

#define CSL_MIBSPI_SPIBUF_RXEMPTY_MASK   (0x80000000u)
#define CSL_MIBSPI_SPIBUF_RXEMPTY_SHIFT  (0x0000001Fu)
#define CSL_MIBSPI_SPIBUF_RXEMPTY_RESETVAL (0x00000001u)
#define CSL_MIBSPI_SPIBUF_RXEMPTY_YES    (0x00000000u)
#define CSL_MIBSPI_SPIBUF_RXEMPTY_NO     (0x00000001u)

#define CSL_MIBSPI_SPIBUF_RXOVR_MASK     (0x40000000u)
#define CSL_MIBSPI_SPIBUF_RXOVR_SHIFT    (0x0000001Eu)
#define CSL_MIBSPI_SPIBUF_RXOVR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIBUF_RXOVR_NO       (0x00000000u)
#define CSL_MIBSPI_SPIBUF_RXOVR_YES      (0x00000001u)

#define CSL_MIBSPI_SPIBUF_TXFULL_MASK    (0x20000000u)
#define CSL_MIBSPI_SPIBUF_TXFULL_SHIFT   (0x0000001Du)
#define CSL_MIBSPI_SPIBUF_TXFULL_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIBUF_TXFULL_NO      (0x00000000u)
#define CSL_MIBSPI_SPIBUF_TXFULL_YES     (0x00000001u)

#define CSL_MIBSPI_SPIBUF_BITERR_MASK    (0x10000000u)
#define CSL_MIBSPI_SPIBUF_BITERR_SHIFT   (0x0000001Cu)
#define CSL_MIBSPI_SPIBUF_BITERR_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIBUF_BITERR_NO      (0x00000000u)
#define CSL_MIBSPI_SPIBUF_BITERR_YES     (0x00000001u)

#define CSL_MIBSPI_SPIBUF_DESYNC_MASK    (0x08000000u)
#define CSL_MIBSPI_SPIBUF_DESYNC_SHIFT   (0x0000001Bu)
#define CSL_MIBSPI_SPIBUF_DESYNC_RESETVAL (0x00000000u)
#define CSL_MIBSPI_SPIBUF_DESYNC_NO      (0x00000000u)
#define CSL_MIBSPI_SPIBUF_DESYNC_YES     (0x00000001u)

#define CSL_MIBSPI_SPIBUF_PARITYERR_MASK (0x04000000u)
#define CSL_MIBSPI_SPIBUF_PARITYERR_SHIFT (0x0000001Au)
#define CSL_MIBSPI_SPIBUF_PARITYERR_RESETVAL (0x00000000u)
1234

cslr_mibspi.h - 源码说明

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