irda.tan.qmsg

在FPGA上开发红外传输接口

{ "Info" "ITDB_FULL_TCO_RESULT" "clk ir_tx lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 12.900 ns register " "Info: tco from clock clk to destination pin ir_tx through register lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] is 12.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 41 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 41; CLK Node = 'clk'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC5_D9 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_D9; Fanout = 2; REG Node = 'lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "0.400 ns" { clk lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "2.400 ns" { clk lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest register pin " "Info: + Longest register to pin delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC5_D9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D9; Fanout = 2; REG Node = 'lpm_counter:pulse_cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "e:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.600 ns) 2.900 ns i113~21 2 COMB LC2_D2 1 " "Info: 2: + IC(1.300 ns) + CELL(1.600 ns) = 2.900 ns; Loc. = LC2_D2; Fanout = 1; COMB Node = 'i113~21'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "2.900 ns" { lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] i113~21 } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 10.000 ns ir_tx 3 PIN Pin_157 0 " "Info: 3: + IC(0.800 ns) + CELL(6.300 ns) = 10.000 ns; Loc. = Pin_157; Fanout = 0; PIN Node = 'ir_tx'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "7.100 ns" { i113~21 ir_tx } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.900 ns 79.00 % " "Info: Total cell delay = 7.900 ns ( 79.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 21.00 % " "Info: Total interconnect delay = 2.100 ns ( 21.00 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "10.000 ns" { lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] i113~21 ir_tx } "NODE_NAME" } } }  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "2.400 ns" { clk lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } } { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "10.000 ns" { lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] i113~21 ir_tx } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "keyin led 16.300 ns Longest " "Info: Longest tpd from source pin keyin to destination pin led is 16.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns keyin 1 PIN Pin_89 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_89; Fanout = 1; PIN Node = 'keyin'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { keyin } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.400 ns) 9.100 ns led~0 2 COMB LC2_A20 1 " "Info: 2: + IC(2.800 ns) + CELL(1.400 ns) = 9.100 ns; Loc. = LC2_A20; Fanout = 1; COMB Node = 'led~0'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "4.200 ns" { keyin led~0 } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(6.300 ns) 16.300 ns led 3 PIN Pin_73 0 " "Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 16.300 ns; Loc. = Pin_73; Fanout = 0; PIN Node = 'led'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "7.200 ns" { led~0 led } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.600 ns 77.30 % " "Info: Total cell delay = 12.600 ns ( 77.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns 22.70 % " "Info: Total interconnect delay = 3.700 ns ( 22.70 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "16.300 ns" { keyin led~0 led } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk ir_tx tx_en 11.700 ns register " "Info: Minimum tco from clock clk to destination pin ir_tx through register tx_en is 11.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK Pin_79 41 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_79; Fanout = 41; CLK Node = 'clk'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns tx_en 2 REG LC3_D2 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_D2; Fanout = 2; REG Node = 'tx_en'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "0.400 ns" { clk tx_en } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "2.400 ns" { clk tx_en } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 50 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.800 ns + Shortest register pin " "Info: + Shortest register to pin delay is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tx_en 1 REG LC3_D2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D2; Fanout = 2; REG Node = 'tx_en'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { tx_en } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 1.700 ns i113~21 2 COMB LC2_D2 1 " "Info: 2: + IC(0.300 ns) + CELL(1.400 ns) = 1.700 ns; Loc. = LC2_D2; Fanout = 1; COMB Node = 'i113~21'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "1.700 ns" { tx_en i113~21 } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 8.800 ns ir_tx 3 PIN Pin_157 0 " "Info: 3: + IC(0.800 ns) + CELL(6.300 ns) = 8.800 ns; Loc. = Pin_157; Fanout = 0; PIN Node = 'ir_tx'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "7.100 ns" { i113~21 ir_tx } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns 87.50 % " "Info: Total cell delay = 7.700 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 12.50 % " "Info: Total interconnect delay = 1.100 ns ( 12.50 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "8.800 ns" { tx_en i113~21 ir_tx } "NODE_NAME" } } }  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "2.400 ns" { clk tx_en } "NODE_NAME" } } } { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "8.800 ns" { tx_en i113~21 ir_tx } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ir_rx led1 15.800 ns Shortest " "Info: Shortest tpd from source pin ir_rx to destination pin led1 is 15.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns ir_rx 1 PIN Pin_150 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_150; Fanout = 1; PIN Node = 'ir_rx'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "" { ir_rx } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.400 ns) 8.600 ns led1~0 2 COMB LC1_A20 1 " "Info: 2: + IC(2.300 ns) + CELL(1.400 ns) = 8.600 ns; Loc. = LC1_A20; Fanout = 1; COMB Node = 'led1~0'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "3.700 ns" { ir_rx led1~0 } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(6.300 ns) 15.800 ns led1 3 PIN Pin_74 0 " "Info: 3: + IC(0.900 ns) + CELL(6.300 ns) = 15.800 ns; Loc. = Pin_74; Fanout = 0; PIN Node = 'led1'" {  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "7.200 ns" { led1~0 led1 } "NODE_NAME" } } } { "F:/work/irda/irda.v" "" "" { Text "F:/work/irda/irda.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.600 ns 79.75 % " "Info: Total cell delay = 12.600 ns ( 79.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 20.25 % " "Info: Total interconnect delay = 3.200 ns ( 20.25 % )" {  } {  } 0}  } { { "F:/work/irda/db/irda_cmp.qrpt" "" "" { Report "F:/work/irda/db/irda_cmp.qrpt" Compiler "irda" "UNKNOWN" "V1" "F:/work/irda/db/irda.quartus_db" { Floorplan "" "" "15.800 ns" { ir_rx led1~0 led1 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 05 17:43:02 2005 " "Info: Processing ended: Sun Jun 05 17:43:02 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}