irda.tan.rpt

在FPGA上开发红外传输接口

; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                              ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                      ; From                                                            ; To                                                             ;
+------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------+----------------------------------------------------------------+
; Worst-case tco         ; N/A   ; None          ; 12.900 ns                        ; lpm_counter:pulse_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; ir_tx                                                          ;
; Worst-case tpd         ; N/A   ; None          ; 16.300 ns                        ; keyin                                                           ; led                                                            ;
; Worst-case minimum tco ; N/A   ; None          ; 11.700 ns                        ; tx_en                                                           ; ir_tx                                                          ;
; Worst-case minimum tpd ; N/A   ; None          ; 15.800 ns                        ; ir_rx                                                           ; led1                                                           ;
; Clock Setup: 'clk'     ; N/A   ; None          ; 90.91 MHz ( period = 11.000 ns ) ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[7] ;
+------------------------+-------+---------------+----------------------------------+-----------------------------------------------------------------+----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                   ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                            ; To                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-----------------------------------------------------------------+-----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[1]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[2]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[4]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[5]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[6]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[7]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[2]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                           ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[1]  ; lpm_counter:slow_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; None                    ;