fred.tan.rpt

用FPGA仿真实现数控分频器

; N/A   ; None         ; 0.404 ns   ; num[2] ; dats[1]   ; clk      ;
; N/A   ; None         ; 0.398 ns   ; num[2] ; dats[0]   ; clk      ;
; N/A   ; None         ; 0.343 ns   ; num[0] ; dats[2]   ; clk      ;
; N/A   ; None         ; 0.313 ns   ; num[3] ; fout~reg0 ; clk      ;
; N/A   ; None         ; 0.118 ns   ; num[2] ; dats[2]   ; clk      ;
; N/A   ; None         ; 0.038 ns   ; num[0] ; fout~reg0 ; clk      ;
; N/A   ; None         ; -0.187 ns  ; num[2] ; fout~reg0 ; clk      ;
; N/A   ; None         ; -0.525 ns  ; num[1] ; dats[3]   ; clk      ;
; N/A   ; None         ; -0.526 ns  ; num[1] ; dats[1]   ; clk      ;
; N/A   ; None         ; -0.532 ns  ; num[1] ; dats[0]   ; clk      ;
; N/A   ; None         ; -0.812 ns  ; num[1] ; dats[2]   ; clk      ;
; N/A   ; None         ; -1.138 ns  ; num[1] ; fout~reg0 ; clk      ;
+-------+--------------+------------+--------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 15.115 ns  ; fout~reg0 ; fout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+--------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To        ; To Clock ;
+---------------+-------------+-----------+--------+-----------+----------+
; N/A           ; None        ; 1.190 ns  ; num[1] ; fout~reg0 ; clk      ;
; N/A           ; None        ; 0.864 ns  ; num[1] ; dats[2]   ; clk      ;
; N/A           ; None        ; 0.584 ns  ; num[1] ; dats[0]   ; clk      ;
; N/A           ; None        ; 0.578 ns  ; num[1] ; dats[1]   ; clk      ;
; N/A           ; None        ; 0.577 ns  ; num[1] ; dats[3]   ; clk      ;
; N/A           ; None        ; 0.239 ns  ; num[2] ; fout~reg0 ; clk      ;
; N/A           ; None        ; 0.014 ns  ; num[0] ; fout~reg0 ; clk      ;
; N/A           ; None        ; -0.066 ns ; num[2] ; dats[2]   ; clk      ;
; N/A           ; None        ; -0.261 ns ; num[3] ; fout~reg0 ; clk      ;
; N/A           ; None        ; -0.291 ns ; num[0] ; dats[2]   ; clk      ;
; N/A           ; None        ; -0.346 ns ; num[2] ; dats[0]   ; clk      ;
; N/A           ; None        ; -0.352 ns ; num[2] ; dats[1]   ; clk      ;
; N/A           ; None        ; -0.353 ns ; num[2] ; dats[3]   ; clk      ;
; N/A           ; None        ; -0.571 ns ; num[0] ; dats[0]   ; clk      ;
; N/A           ; None        ; -0.577 ns ; num[0] ; dats[1]   ; clk      ;
; N/A           ; None        ; -0.578 ns ; num[0] ; dats[3]   ; clk      ;
; N/A           ; None        ; -0.604 ns ; num[3] ; dats[2]   ; clk      ;
; N/A           ; None        ; -0.884 ns ; num[3] ; dats[0]   ; clk      ;
; N/A           ; None        ; -0.890 ns ; num[3] ; dats[1]   ; clk      ;
; N/A           ; None        ; -0.891 ns ; num[3] ; dats[3]   ; clk      ;
+---------------+-------------+-----------+--------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jan 05 15:24:46 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fred -c fred --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "dats[3]" and destination register "dats[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.482 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
            Info: 2: + IC(0.554 ns) + CELL(0.114 ns) = 0.668 ns; Loc. = LC_X34_Y19_N9; Fanout = 2; COMB Node = 'Equal0~39'
            Info: 3: + IC(0.446 ns) + CELL(0.590 ns) = 1.704 ns; Loc. = LC_X34_Y19_N1; Fanout = 4; COMB Node = 'Equal0~40'
            Info: 4: + IC(0.469 ns) + CELL(0.309 ns) = 2.482 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
            Info: Total cell delay = 1.013 ns ( 40.81 % )
            Info: Total interconnect delay = 1.469 ns ( 59.19 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 7.778 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
                Info: Total cell delay = 2.180 ns ( 28.03 % )
                Info: Total interconnect delay = 5.598 ns ( 71.97 % )
            Info: - Longest clock path from clock "clk" to source register is 7.778 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
                Info: Total cell delay = 2.180 ns ( 28.03 % )
                Info: Total interconnect delay = 5.598 ns ( 71.97 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "dats[3]" (data pin = "num[3]", clock pin = "clk") is 0.943 ns
    Info: + Longest pin to register delay is 8.684 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_168; Fanout = 1; PIN Node = 'num[3]'
        Info: 2: + IC(5.109 ns) + CELL(0.292 ns) = 6.870 ns; Loc. = LC_X34_Y19_N9; Fanout = 2; COMB Node = 'Equal0~39'
        Info: 3: + IC(0.446 ns) + CELL(0.590 ns) = 7.906 ns; Loc. = LC_X34_Y19_N1; Fanout = 4; COMB Node = 'Equal0~40'
        Info: 4: + IC(0.469 ns) + CELL(0.309 ns) = 8.684 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
        Info: Total cell delay = 2.660 ns ( 30.63 % )
        Info: Total interconnect delay = 6.024 ns ( 69.37 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 7.778 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats[3]'
        Info: Total cell delay = 2.180 ns ( 28.03 % )
        Info: Total interconnect delay = 5.598 ns ( 71.97 % )
Info: tco from clock "clk" to destination pin "fout" through register "fout~reg0" is 15.115 ns
    Info: + Longest clock path from clock "clk" to source register is 7.778 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'
        Info: Total cell delay = 2.180 ns ( 28.03 % )
        Info: Total interconnect delay = 5.598 ns ( 71.97 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.113 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'
        Info: 2: + IC(5.005 ns) + CELL(2.108 ns) = 7.113 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'fout'
        Info: Total cell delay = 2.108 ns ( 29.64 % )
        Info: Total interconnect delay = 5.005 ns ( 70.36 % )
Info: th for register "fout~reg0" (data pin = "num[1]", clock pin = "clk") is 1.190 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.778 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'
        Info: Total cell delay = 2.180 ns ( 28.03 % )
        Info: Total interconnect delay = 5.598 ns ( 71.97 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.603 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_177; Fanout = 2; PIN Node = 'num[1]'
        Info: 2: + IC(4.527 ns) + CELL(0.607 ns) = 6.603 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'
        Info: Total cell delay = 2.076 ns ( 31.44 % )
        Info: Total interconnect delay = 4.527 ns ( 68.56 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jan 05 15:24:47 2007
    Info: Elapsed time: 00:00:02