fred.tan.qmsg

用FPGA仿真实现数控分频器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register dats\[3\] dats\[3\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"dats\[3\]\" and destination register \"dats\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.482 ns + Longest register register " "Info: + Longest register to register delay is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dats\[3\] 1 REG LC_X34_Y19_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.114 ns) 0.668 ns Equal0~39 2 COMB LC_X34_Y19_N9 2 " "Info: 2: + IC(0.554 ns) + CELL(0.114 ns) = 0.668 ns; Loc. = LC_X34_Y19_N9; Fanout = 2; COMB Node = 'Equal0~39'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.668 ns" { dats[3] Equal0~39 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.590 ns) 1.704 ns Equal0~40 3 COMB LC_X34_Y19_N1 4 " "Info: 3: + IC(0.446 ns) + CELL(0.590 ns) = 1.704 ns; Loc. = LC_X34_Y19_N1; Fanout = 4; COMB Node = 'Equal0~40'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.036 ns" { Equal0~39 Equal0~40 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.469 ns) + CELL(0.309 ns) 2.482 ns dats\[3\] 4 REG LC_X34_Y19_N5 2 " "Info: 4: + IC(0.469 ns) + CELL(0.309 ns) = 2.482 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { Equal0~40 dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.013 ns ( 40.81 % ) " "Info: Total cell delay = 1.013 ns ( 40.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.469 ns ( 59.19 % ) " "Info: Total interconnect delay = 1.469 ns ( 59.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.482 ns" { dats[3] Equal0~39 Equal0~40 dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.482 ns" { dats[3] Equal0~39 Equal0~40 dats[3] } { 0.000ns 0.554ns 0.446ns 0.469ns } { 0.000ns 0.114ns 0.590ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.778 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.711 ns) 7.778 ns dats\[3\] 2 REG LC_X34_Y19_N5 2 " "Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.309 ns" { clk dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.03 % ) " "Info: Total cell delay = 2.180 ns ( 28.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 71.97 % ) " "Info: Total interconnect delay = 5.598 ns ( 71.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.778 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.711 ns) 7.778 ns dats\[3\] 2 REG LC_X34_Y19_N5 2 " "Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.309 ns" { clk dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.03 % ) " "Info: Total cell delay = 2.180 ns ( 28.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 71.97 % ) " "Info: Total interconnect delay = 5.598 ns ( 71.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.482 ns" { dats[3] Equal0~39 Equal0~40 dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.482 ns" { dats[3] Equal0~39 Equal0~40 dats[3] } { 0.000ns 0.554ns 0.446ns 0.469ns } { 0.000ns 0.114ns 0.590ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { dats[3] } {  } {  } } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dats\[3\] num\[3\] clk 0.943 ns register " "Info: tsu for register \"dats\[3\]\" (data pin = \"num\[3\]\", clock pin = \"clk\") is 0.943 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.684 ns + Longest pin register " "Info: + Longest pin to register delay is 8.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns num\[3\] 1 PIN PIN_168 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_168; Fanout = 1; PIN Node = 'num\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { num[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.109 ns) + CELL(0.292 ns) 6.870 ns Equal0~39 2 COMB LC_X34_Y19_N9 2 " "Info: 2: + IC(5.109 ns) + CELL(0.292 ns) = 6.870 ns; Loc. = LC_X34_Y19_N9; Fanout = 2; COMB Node = 'Equal0~39'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.401 ns" { num[3] Equal0~39 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.590 ns) 7.906 ns Equal0~40 3 COMB LC_X34_Y19_N1 4 " "Info: 3: + IC(0.446 ns) + CELL(0.590 ns) = 7.906 ns; Loc. = LC_X34_Y19_N1; Fanout = 4; COMB Node = 'Equal0~40'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.036 ns" { Equal0~39 Equal0~40 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.469 ns) + CELL(0.309 ns) 8.684 ns dats\[3\] 4 REG LC_X34_Y19_N5 2 " "Info: 4: + IC(0.469 ns) + CELL(0.309 ns) = 8.684 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { Equal0~40 dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.660 ns ( 30.63 % ) " "Info: Total cell delay = 2.660 ns ( 30.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.024 ns ( 69.37 % ) " "Info: Total interconnect delay = 6.024 ns ( 69.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.684 ns" { num[3] Equal0~39 Equal0~40 dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.684 ns" { num[3] num[3]~out0 Equal0~39 Equal0~40 dats[3] } { 0.000ns 0.000ns 5.109ns 0.446ns 0.469ns } { 0.000ns 1.469ns 0.292ns 0.590ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.778 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.711 ns) 7.778 ns dats\[3\] 2 REG LC_X34_Y19_N5 2 " "Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N5; Fanout = 2; REG Node = 'dats\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.309 ns" { clk dats[3] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.03 % ) " "Info: Total cell delay = 2.180 ns ( 28.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 71.97 % ) " "Info: Total interconnect delay = 5.598 ns ( 71.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.684 ns" { num[3] Equal0~39 Equal0~40 dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.684 ns" { num[3] num[3]~out0 Equal0~39 Equal0~40 dats[3] } { 0.000ns 0.000ns 5.109ns 0.446ns 0.469ns } { 0.000ns 1.469ns 0.292ns 0.590ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk dats[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 dats[3] } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout fout~reg0 15.115 ns register " "Info: tco from clock \"clk\" to destination pin \"fout\" through register \"fout~reg0\" is 15.115 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.778 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.711 ns) 7.778 ns fout~reg0 2 REG LC_X34_Y19_N1 1 " "Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.309 ns" { clk fout~reg0 } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.03 % ) " "Info: Total cell delay = 2.180 ns ( 28.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 71.97 % ) " "Info: Total interconnect delay = 5.598 ns ( 71.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.113 ns + Longest register pin " "Info: + Longest register to pin delay is 7.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fout~reg0 1 REG LC_X34_Y19_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fout~reg0 } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.005 ns) + CELL(2.108 ns) 7.113 ns fout 2 PIN PIN_79 0 " "Info: 2: + IC(5.005 ns) + CELL(2.108 ns) = 7.113 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'fout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.113 ns" { fout~reg0 fout } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 29.64 % ) " "Info: Total cell delay = 2.108 ns ( 29.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.005 ns ( 70.36 % ) " "Info: Total interconnect delay = 5.005 ns ( 70.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.113 ns" { fout~reg0 fout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.113 ns" { fout~reg0 fout } { 0.000ns 5.005ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.113 ns" { fout~reg0 fout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.113 ns" { fout~reg0 fout } { 0.000ns 5.005ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fout~reg0 num\[1\] clk 1.190 ns register " "Info: th for register \"fout~reg0\" (data pin = \"num\[1\]\", clock pin = \"clk\") is 1.190 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.778 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.711 ns) 7.778 ns fout~reg0 2 REG LC_X34_Y19_N1 1 " "Info: 2: + IC(5.598 ns) + CELL(0.711 ns) = 7.778 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.309 ns" { clk fout~reg0 } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.03 % ) " "Info: Total cell delay = 2.180 ns ( 28.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.598 ns ( 71.97 % ) " "Info: Total interconnect delay = 5.598 ns ( 71.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.603 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns num\[1\] 1 PIN PIN_177 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_177; Fanout = 2; PIN Node = 'num\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { num[1] } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.527 ns) + CELL(0.607 ns) 6.603 ns fout~reg0 2 REG LC_X34_Y19_N1 1 " "Info: 2: + IC(4.527 ns) + CELL(0.607 ns) = 6.603 ns; Loc. = LC_X34_Y19_N1; Fanout = 1; REG Node = 'fout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.134 ns" { num[1] fout~reg0 } "NODE_NAME" } } { "../../../EDAfile/fredevide/fred.vhd" "" { Text "E:/dongjicheng/EDAfile/fredevide/fred.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 31.44 % ) " "Info: Total cell delay = 2.076 ns ( 31.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.527 ns ( 68.56 % ) " "Info: Total interconnect delay = 4.527 ns ( 68.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.603 ns" { num[1] fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.603 ns" { num[1] num[1]~out0 fout~reg0 } { 0.000ns 0.000ns 4.527ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.778 ns" { clk fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.778 ns" { clk clk~out0 fout~reg0 } { 0.000ns 0.000ns 5.598ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.603 ns" { num[1] fout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.603 ns" { num[1] num[1]~out0 fout~reg0 } { 0.000ns 0.000ns 4.527ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}