disp.vhd

在QuartusII里用VHDL仿真实现电梯控制器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity disp is
  port(clk_100Hz : in std_logic;
       data      : in integer range 1 to 3;
       segout    : out std_logic_vector(6 downto 0));
end entity;

architecture art of disp is
  begin
  process(clk_100Hz)
    begin
    if clk_100Hz'event and clk_100Hz='1' then
       case data is
         when 1 => segout<="0000110";
         when 2 => segout<="1011011";
         when 3 => segout<="1001111";
         when others => null;
       end case; 
    end if;
  end process;
end art;