lift.tan.qmsg

在QuartusII里用VHDL仿真实现电梯控制器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk upsiglight udsig 15.700 ns register " "Info: tco from clock \"clk\" to destination pin \"upsiglight\" through register \"udsig\" is 15.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns fen:u1\|ck1 2 REG LC36 13 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC36; Fanout = 13; REG Node = 'fen:u1\|ck1'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk fen:u1|ck1 } "NODE_NAME" } } { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns udsig 3 REG LC3 14 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC3; Fanout = 14; REG Node = 'udsig'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { fen:u1|ck1 udsig } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 80.72 % ) " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 19.28 % ) " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 udsig } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 udsig } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register pin " "Info: + Longest register to pin delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns udsig 1 REG LC3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 14; REG Node = 'udsig'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { udsig } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.000 ns) 5.600 ns udsig~420 2 COMB LC29 1 " "Info: 2: + IC(1.600 ns) + CELL(4.000 ns) = 5.600 ns; Loc. = LC29; Fanout = 1; COMB Node = 'udsig~420'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { udsig udsig~420 } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 6.000 ns upsiglight 3 PIN PIN_15 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 6.000 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'upsiglight'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { udsig~420 upsiglight } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns ( 73.33 % ) " "Info: Total cell delay = 4.400 ns ( 73.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 26.67 % ) " "Info: Total interconnect delay = 1.600 ns ( 26.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { udsig udsig~420 upsiglight } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { udsig udsig~420 upsiglight } { 0.000ns 1.600ns 0.000ns } { 0.000ns 4.000ns 0.400ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 udsig } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 udsig } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { udsig udsig~420 upsiglight } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { udsig udsig~420 upsiglight } { 0.000ns 1.600ns 0.000ns } { 0.000ns 4.000ns 0.400ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fdnlight\[3\]~reg0 f3dnbutton clk 5.400 ns register " "Info: th for register \"fdnlight\[3\]~reg0\" (data pin = \"f3dnbutton\", clock pin = \"clk\") is 5.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns fen:u1\|ck2 2 REG LC34 11 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC34; Fanout = 11; REG Node = 'fen:u1\|ck2'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk fen:u1|ck2 } "NODE_NAME" } } { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns fdnlight\[3\]~reg0 3 REG LC57 21 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC57; Fanout = 21; REG Node = 'fdnlight\[3\]~reg0'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { fen:u1|ck2 fdnlight[3]~reg0 } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 80.72 % ) " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 19.28 % ) " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck2 fdnlight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck2 fdnlight[3]~reg0 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f3dnbutton 1 PIN PIN_68 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_68; Fanout = 1; PIN Node = 'f3dnbutton'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { f3dnbutton } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 4.600 ns fdnlight\[3\]~reg0 2 REG LC57 21 " "Info: 2: + IC(1.400 ns) + CELL(3.000 ns) = 4.600 ns; Loc. = LC57; Fanout = 21; REG Node = 'fdnlight\[3\]~reg0'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { f3dnbutton fdnlight[3]~reg0 } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 69.57 % ) " "Info: Total cell delay = 3.200 ns ( 69.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 30.43 % ) " "Info: Total interconnect delay = 1.400 ns ( 30.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { f3dnbutton fdnlight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { f3dnbutton f3dnbutton~out fdnlight[3]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck2 fdnlight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck2 fdnlight[3]~reg0 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { f3dnbutton fdnlight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { f3dnbutton f3dnbutton~out fdnlight[3]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "97 " "Info: Allocated 97 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 03 15:39:17 2007 " "Info: Processing ended: Tue Jul 03 15:39:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}