lift.tan.qmsg

在QuartusII里用VHDL仿真实现电梯控制器

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } } { "g:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|ck1 " "Info: Detected ripple clock \"fen:u1\|ck1\" as buffer" {  } { { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } } { "g:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|ck1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|ck2 " "Info: Detected ripple clock \"fen:u1\|ck2\" as buffer" {  } { { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } } { "g:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|ck2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register stoplight\[3\]~reg0 register mylift.state_bit_1 77.52 MHz 12.9 ns Internal " "Info: Clock \"clk\" has Internal fmax of 77.52 MHz between source register \"stoplight\[3\]~reg0\" and destination register \"mylift.state_bit_1\" (period= 12.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.500 ns + Longest register register " "Info: + Longest register to register delay is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns stoplight\[3\]~reg0 1 REG LC73 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC73; Fanout = 16; REG Node = 'stoplight\[3\]~reg0'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { stoplight[3]~reg0 } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.700 ns) 5.300 ns ctrlift~200sexp 2 COMB SEXP2 2 " "Info: 2: + IC(1.600 ns) + CELL(3.700 ns) = 5.300 ns; Loc. = SEXP2; Fanout = 2; COMB Node = 'ctrlift~200sexp'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { stoplight[3]~reg0 ctrlift~200sexp } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 8.300 ns mylift.state_bit_1~574 3 COMB LC4 1 " "Info: 3: + IC(0.000 ns) + CELL(3.000 ns) = 8.300 ns; Loc. = LC4; Fanout = 1; COMB Node = 'mylift.state_bit_1~574'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { ctrlift~200sexp mylift.state_bit_1~574 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 9.400 ns mylift.state_bit_1~579 4 COMB LC5 1 " "Info: 4: + IC(0.000 ns) + CELL(1.100 ns) = 9.400 ns; Loc. = LC5; Fanout = 1; COMB Node = 'mylift.state_bit_1~579'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { mylift.state_bit_1~574 mylift.state_bit_1~579 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 10.500 ns mylift.state_bit_1 5 REG LC6 57 " "Info: 5: + IC(0.000 ns) + CELL(1.100 ns) = 10.500 ns; Loc. = LC6; Fanout = 57; REG Node = 'mylift.state_bit_1'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { mylift.state_bit_1~579 mylift.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.900 ns ( 84.76 % ) " "Info: Total cell delay = 8.900 ns ( 84.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 15.24 % ) " "Info: Total interconnect delay = 1.600 ns ( 15.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { stoplight[3]~reg0 ctrlift~200sexp mylift.state_bit_1~574 mylift.state_bit_1~579 mylift.state_bit_1 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { stoplight[3]~reg0 ctrlift~200sexp mylift.state_bit_1~574 mylift.state_bit_1~579 mylift.state_bit_1 } { 0.000ns 1.600ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.700ns 3.000ns 1.100ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns fen:u1\|ck1 2 REG LC36 13 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC36; Fanout = 13; REG Node = 'fen:u1\|ck1'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk fen:u1|ck1 } "NODE_NAME" } } { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns mylift.state_bit_1 3 REG LC6 57 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC6; Fanout = 57; REG Node = 'mylift.state_bit_1'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { fen:u1|ck1 mylift.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 80.72 % ) " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 19.28 % ) " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 mylift.state_bit_1 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 mylift.state_bit_1 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns fen:u1\|ck2 2 REG LC34 11 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC34; Fanout = 11; REG Node = 'fen:u1\|ck2'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk fen:u1|ck2 } "NODE_NAME" } } { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns stoplight\[3\]~reg0 3 REG LC73 16 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC73; Fanout = 16; REG Node = 'stoplight\[3\]~reg0'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { fen:u1|ck2 stoplight[3]~reg0 } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 80.72 % ) " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 19.28 % ) " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck2 stoplight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck2 stoplight[3]~reg0 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 mylift.state_bit_1 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 mylift.state_bit_1 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck2 stoplight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck2 stoplight[3]~reg0 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" {  } { { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 192 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { stoplight[3]~reg0 ctrlift~200sexp mylift.state_bit_1~574 mylift.state_bit_1~579 mylift.state_bit_1 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { stoplight[3]~reg0 ctrlift~200sexp mylift.state_bit_1~574 mylift.state_bit_1~579 mylift.state_bit_1 } { 0.000ns 1.600ns 0.000ns 0.000ns 0.000ns } { 0.000ns 3.700ns 3.000ns 1.100ns 1.100ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 mylift.state_bit_1 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 mylift.state_bit_1 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck2 stoplight[3]~reg0 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck2 stoplight[3]~reg0 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "comb~7 reset clk -2.400 ns register " "Info: tsu for register \"comb~7\" (data pin = \"reset\", clock pin = \"clk\") is -2.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns + Longest pin register " "Info: + Longest pin to register delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns reset 1 PIN PIN_74 33 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_74; Fanout = 33; PIN Node = 'reset'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(3.000 ns) 4.900 ns comb~7 2 REG LC2 28 " "Info: 2: + IC(1.700 ns) + CELL(3.000 ns) = 4.900 ns; Loc. = LC2; Fanout = 28; REG Node = 'comb~7'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { reset comb~7 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 65.31 % ) " "Info: Total cell delay = 3.200 ns ( 65.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 34.69 % ) " "Info: Total interconnect delay = 1.700 ns ( 34.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { reset comb~7 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { reset reset~out comb~7 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 0.200ns 3.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'clk'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threelift.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/threelift.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.600 ns fen:u1\|ck1 2 REG LC36 13 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.600 ns; Loc. = LC36; Fanout = 13; REG Node = 'fen:u1\|ck1'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { clk fen:u1|ck1 } "NODE_NAME" } } { "fen.vhd" "" { Text "D:/ALTERA/项目实践/eda项目实践--电梯控制器的设计/QuartusII工程文件夹/fen.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.100 ns) 8.300 ns comb~7 3 REG LC2 28 " "Info: 3: + IC(1.600 ns) + CELL(3.100 ns) = 8.300 ns; Loc. = LC2; Fanout = 28; REG Node = 'comb~7'" {  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { fen:u1|ck1 comb~7 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.700 ns ( 80.72 % ) " "Info: Total cell delay = 6.700 ns ( 80.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 19.28 % ) " "Info: Total interconnect delay = 1.600 ns ( 19.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 comb~7 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 comb~7 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { reset comb~7 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.900 ns" { reset reset~out comb~7 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 0.200ns 3.000ns } "" } } { "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { clk fen:u1|ck1 comb~7 } "NODE_NAME" } } { "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { clk clk~out fen:u1|ck1 comb~7 } { 0.000ns 0.000ns 0.000ns 1.600ns } { 0.000ns 1.600ns 2.000ns 3.100ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}