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📁 在QuartusII里用VHDL仿真实现电梯控制器
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        (PORT pterm1[12] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[10] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[11] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[12] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[13\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[14\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[4] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[5] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[10] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[11] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[12] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[13] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[10] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[11] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[12] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[13] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[14\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[15\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[4] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[5] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[6] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[10] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[11] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[12] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[13] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[14] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[10] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[11] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[12] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[13] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[14] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[15\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|ck2\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|ck2\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (PORT pena[0] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[1] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[2] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[3] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[4] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[5] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[6] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[7] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[8] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[9] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[10] (4400:4400:4400) (4400:4400:4400))
        (PORT pena[11] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[12] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[13] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[14] (4500:4500:4500) (4500:4500:4500))
        (PORT pena[15] (4500:4500:4500) (4500:4500:4500))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (SETUP pena[0] (posedge clk) (1000:1000:1000))
      (SETUP pena[1] (posedge clk) (1000:1000:1000))
      (SETUP pena[2] (posedge clk) (1000:1000:1000))
      (SETUP pena[3] (posedge clk) (1000:1000:1000))
      (SETUP pena[4] (posedge clk) (1000:1000:1000))
      (SETUP pena[5] (posedge clk) (1000:1000:1000))
      (SETUP pena[6] (posedge clk) (1000:1000:1000))
      (SETUP pena[7] (posedge clk) (1000:1000:1000))
      (SETUP pena[8] (posedge clk) (1000:1000:1000))
      (SETUP pena[9] (posedge clk) (1000:1000:1000))
      (SETUP pena[10] (posedge clk) (1000:1000:1000))
      (SETUP pena[11] (posedge clk) (1000:1000:1000))
      (SETUP pena[12] (posedge clk) (1000:1000:1000))
      (SETUP pena[13] (posedge clk) (1000:1000:1000))
      (SETUP pena[14] (posedge clk) (1000:1000:1000))
      (SETUP pena[15] (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
      (HOLD pena[0] (posedge clk) (1700:1700:1700))
      (HOLD pena[1] (posedge clk) (1700:1700:1700))
      (HOLD pena[2] (posedge clk) (1700:1700:1700))
      (HOLD pena[3] (posedge clk) (1700:1700:1700))
      (HOLD pena[4] (posedge clk) (1700:1700:1700))
      (HOLD pena[5] (posedge clk) (1700:1700:1700))
      (HOLD pena[6] (posedge clk) (1700:1700:1700))
      (HOLD pena[7] (posedge clk) (1700:1700:1700))
      (HOLD pena[8] (posedge clk) (1700:1700:1700))
      (HOLD pena[9] (posedge clk) (1700:1700:1700))
      (HOLD pena[10] (posedge clk) (1700:1700:1700))
      (HOLD pena[11] (posedge clk) (1700:1700:1700))
      (HOLD pena[12] (posedge clk) (1700:1700:1700))
      (HOLD pena[13] (posedge clk) (1700:1700:1700))
      (HOLD pena[14] (posedge clk) (1700:1700:1700))
      (HOLD pena[15] (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\stoplight\[3\]\~reg0_I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm4[0] (1600:1600:1600) (1600:1600:1600))
        (PORT pterm4[1] (1400:1400:1400) (1400:1400:1400))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\stoplight\[3\]\~reg0_I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT paclr[0] (4700:4700:4700) (4700:4700:4700))
        (PORT pclk[0] (4700:4700:4700) (4700:4700:4700))
        (IOPATH (posedge paclr[0]) regout (2400:2400:2400) (2400:2400:2400))
        (IOPATH (posedge pclk[0]) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (1000:1000:1000))
      (HOLD datain (posedge pclk[0]) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_io")
    (INSTANCE \\f3dnbutton\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio dataout (200:200:200) (200:200:200))
      )
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\fdnlight\[3\]\~reg0_I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm4[0] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm4[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm4[2] (1700:1700:1700) (1700:1700:1700))
        (PORT pterm4[3] (1700:1700:1700) (1700:1700:1700))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm4[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\fdnlight\[3\]\~reg0_I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT paclr[0] (4700:4700:4700) (4700:4700:4700))
        (PORT pclk[0] (4700:4700:4700) (4700:4700:4700))
        (IOPATH (posedge paclr[0]) regout (2400:2400:2400) (2400:2400:2400))
        (IOPATH (posedge pclk[0]) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge pclk[0]) (1000:1000:1000))
      (HOLD datain (posedge pclk[0]) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\stoplight\[1\]\~reg0_I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm0[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm0[1] (1600:1600:1600) (1600:1600:1600))
        (PORT pterm1[0] (1700:1700:1700) (1700:1700:1700))
💿 文件大小 396 K
👤 上传用户 cnnotes
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#QuartusII #VHDL #仿真实现 #电梯控制器
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