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📁 在QuartusII里用VHDL仿真实现电梯控制器
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      (ABSOLUTE
        (PORT pterm1[0] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[2] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[6\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[7\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[2] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[7\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[8\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[2] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[8\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[9\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[2] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[9\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[10\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[10\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[11\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[10] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[10] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[11\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[12\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[4] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[10] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[11] (1500:1500:1500) (1500:1500:1500))
        (IOPATH pterm1[0] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[1] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[2] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[3] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[4] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[5] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[6] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[7] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[8] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[9] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[10] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH pterm1[11] regin (3000:3000:3000) (3000:3000:3000))
        (IOPATH fbkin regin (4400:4400:4400) (4400:4400:4400))
      )
    )
  )
  (CELL
    (CELLTYPE "max_mcell_register")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[12\]\~I\\.preg)
    (DELAY
      (ABSOLUTE
        (PORT clk (600:600:600) (600:600:600))
        (IOPATH (posedge clk) regout (1400:1400:1400) (1400:1400:1400))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (1000:1000:1000))
      (HOLD datain (posedge clk) (1700:1700:1700))
    )
  )
  (CELL
    (CELLTYPE "max_asynch_mcell")
    (INSTANCE \\u1\|cnt2_rtl_1\|dffs\[13\]\~I\\.pcom)
    (DELAY
      (ABSOLUTE
        (PORT pterm1[0] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[1] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[2] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[3] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[4] (1400:1400:1400) (1400:1400:1400))
        (PORT pterm1[5] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[6] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[7] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[8] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[9] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[10] (1500:1500:1500) (1500:1500:1500))
        (PORT pterm1[11] (1500:1500:1500) (1500:1500:1500))
💿 文件大小 396 K
👤 上传用户 cnnotes
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#QuartusII #VHDL #仿真实现 #电梯控制器
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