lift.tan.talkback.xml

在QuartusII里用VHDL仿真实现电梯控制器

<!--
This XML file (created on Fri Apr 06 10:46:38 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>003018ae70dc</host_id>
	<nic_id>003018ae70dc</nic_id>
	<cdrive_id>081ccaa1</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_tan</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Fri Apr 06 10:46:38 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1607</cpu_freq>
	</cpu>
	<ram units="MB">447</ram>
</machine>
<project>D:/ALTERA/电梯控制/lift</project>
<revision>lift</revision>
<compilation_summary>
	<flow_status>Successful - Fri Apr 06 10:46:38 2007</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>lift</revision_name>
	<top_level_entity_name>threelift</top_level_entity_name>
	<family>MAX7000S</family>
	<device>EPM7128SLC84-6</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_macrocells>32 / 128 ( 25 % )</total_macrocells>
	<total_pins>27 / 68 ( 40 % )</total_pins>
</compilation_summary>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Fri Apr 06 10:46:38 2007</info>
	<info>Info: th for register &quot;stoplight[2]~reg0&quot; (data pin = &quot;stop2button&quot;, clock pin = &quot;buttonclk&quot;) is -0.700 ns</info>
	<info>Info: - Shortest pin to register delay is 4.600 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>liftclk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>buttonclk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>3.600 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-0.700 ns</actual>
	</nonclk>
	<clk>
		<name>liftclk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>108.70 MHz ( period = 9.200 ns )</actual>
	</clk>
	<clk>
		<name>buttonclk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>144.93 MHz ( period = 6.900 ns )</actual>
	</clk>
</performance>
</talkback>