bbc.vhd

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-- bbc.vhd
-------此模块对应不同的片选信号，输出不同的要显示的数据
library ieee; 
use ieee.std_logic_1164.all; 
---------------------------------
entity bbc is 
port(bai1,bai0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0); 
sel:in std_logic_vector(2 downto 0); 
q: out std_logic_vector(3 downto 0)); 
end bbc; 
---------------------------------------
architecture bbb_arc of bbc is 
begin 
process(sel) 
begin 
case sel is 
when "000"=>q<=bai0;          ---数码管1和0选择ms输出
when "001"=>q<=bai1;         
when "010"=>q<=sec0;          ---数码管3和2选择s输出 
when "011"=>q<=sec1; 
when "100"=>q<=min0;          ---数码管5和4选择minute输出
when "101"=>q<=min1; 
when "110"=>q<=h0;          ---数码管7和6选择hour输出
when "111"=>q<=h1; 
when others=>q<="111"; 
end case; 
end process; 
end bbb_arc;