aa.vhd

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-- aa.vhd
---此模块产生对数码管的位选信号

library ieee; 
use ieee.std_logic_1164.all; 
---------------------------------
entity aa is 
port(sel:in std_logic_vector(2 downto 0); 
d1,d2,d3,d4:out std_logic); 
end aa; 
---------------------------------------
architecture bbb_arc of aa is 
begin 
process(sel) 
begin 
d1<='0';d2<='0';d3<='0';d4<='0';  ----输入初始值
if sel="010" then
d1<='0';d2<='0';d3<='0';d4<='1';

elsif sel="011" then
d1<='0';d2<='0';d3<='1';d4<='0';

elsif sel="010" then
d1<='0';d2<='1';d3<='0';d4<='0';

elsif sel="010" then
d1<='1';d2<='0';d3<='0';d4<='0';

else d1<='0';d2<='0';d3<='0';d4<='0';

end if;

end process; 
end bbb_arc;