gumdisp.vhd

gum vending machine implementation in vhdl, state machine implementation,

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-- Company: 
-- Engineer:        -- 
-- Create Date:     02/25/2009 
-- Design Name: 
-- Module Name:     gumdisp - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gumdisp is
port (x:in STD_LOGIC_VECTOR(1 DOWNTO 0);
		clk,reset:in STD_LOGIC;
		z:out STD_LOGIC);
end gumdisp;

architecture Behavioral of gumdisp is
type state_type is (s0,s1,s2,s3,s4,s5);
signal y:state_type;
begin
process(reset, clk, x)
	begin
	if reset='0' then y<=s0;
	elsif clk'event and clk='1' then
		case y is
			when s0=>
						if x="00" then 
							y<=s0;
						elsif x="01" then 
							y<=s1;
						elsif x="10" then 
							y<=s2;
						elsif x="11" then
							y<=s5;
						else y<=s0;
						end if;
						z<='0';
			when s1=>
						if x="01" then 
							y<=s2;
						elsif x="10" then
							y<=s3;
						else y<=s0;
						end if;
						z<='0';
			when s2=>
						if x="01" then
							y<=s3;
						elsif x="10" then
							y<=s4;
						else y<=s0;
						end if;
						z<='0';
			when s3=>
						if x="01" then
							y<=s4;
						elsif x="10" then
							y<=s5;
						else y<=s0;
						end if;
						z<='0';
			when s4=>
						if x="01" then
							y<=s5;
						else y<=s0;
						end if;
						z<='0';
			when s5=>
						Z<='1';
				end case;
				end if;
			end process;
			
end Behavioral;