alu.map.rpt
来自「设计带进位算术逻辑运算单元」· RPT 代码 · 共 527 行 · 第 1/4 页
RPT
527 行
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------------+
; alu.bdf ; yes ; User Block Diagram/Schematic File ; D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf ;
; alu181.v ; yes ; User Verilog HDL File ; D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v ;
; 74373b.bdf ; yes ; Megafunction ; d:/program files/quartus/libraries/others/maxplus2/74373b.bdf ;
; lpm_counter1.v ; yes ; Other ; D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/lpm_counter1.v ;
; lpm_counter.tdf ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal72.inc ; yes ; Megafunction ; d:/program files/quartus/libraries/megafunctions/aglobal72.inc ;
; db/cntr_6dh.tdf ; yes ; Auto-Generated Megafunction ; D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 223 ;
; -- Combinational with no register ; 219 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 4 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 98 ;
; -- 3 input functions ; 50 ;
; -- 2 input functions ; 73 ;
; -- 1 input functions ; 2 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 165 ;
; -- arithmetic mode ; 58 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 4 ;
; Total logic cells in carry chains ; 67 ;
; I/O pins ; 43 ;
; Maximum fan-out node ; m ;
; Maximum fan-out ; 48 ;
; Total fan-out ; 722 ;
; Average fan-out ; 2.71 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------+--------------+
; |alu ; 223 (0) ; 4 ; 0 ; 43 ; 0 ; 219 (0) ; 0 (0) ; 4 (0) ; 67 (0) ; 0 (0) ; |alu ; work ;
; |74373b:inst1| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |alu|74373b:inst1 ; work ;
; |74373b:inst2| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |alu|74373b:inst2 ; work ;
; |alu181:inst5| ; 202 (202) ; 0 ; 0 ; 0 ; 0 ; 202 (202) ; 0 (0) ; 0 (0) ; 63 (63) ; 0 (0) ; |alu|alu181:inst5 ; work ;
; |lpm_counter1:inst8| ; 5 (0) ; 4 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |alu|lpm_counter1:inst8 ; work ;
; |lpm_counter:lpm_counter_component| ; 5 (0) ; 4 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component ; work ;
; |cntr_6dh:auto_generated| ; 5 (5) ; 4 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated ; work ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; 74373b:inst1|19 ; aclk ; yes ;
; 74373b:inst1|18 ; aclk ; yes ;
; 74373b:inst1|17 ; aclk ; yes ;
; 74373b:inst1|16 ; aclk ; yes ;
; 74373b:inst1|15 ; aclk ; yes ;
; 74373b:inst1|14 ; aclk ; yes ;
; 74373b:inst1|13 ; aclk ; yes ;
; 74373b:inst1|12 ; aclk ; yes ;
; 74373b:inst2|19 ; bclk ; yes ;
; 74373b:inst2|18 ; bclk ; yes ;
; 74373b:inst2|17 ; bclk ; yes ;
; 74373b:inst2|16 ; bclk ; yes ;
; 74373b:inst2|15 ; bclk ; yes ;
; 74373b:inst2|14 ; bclk ; yes ;
; 74373b:inst2|13 ; bclk ; yes ;
; 74373b:inst2|12 ; bclk ; yes ;
; Number of user-specified and inferred latches = 16 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+---+
; Logic Cell Name ; ;
+--------------------------------------------------------+---+
; alu181:inst5|F[7] ; ;
; alu181:inst5|F[6] ; ;
; alu181:inst5|F[5] ; ;
; alu181:inst5|F[4] ; ;
; alu181:inst5|F[3] ; ;
; alu181:inst5|F[2] ; ;
; alu181:inst5|F[1] ; ;
; alu181:inst5|F[0] ; ;
; Number of logic cells representing combinational loops ; 8 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; inst ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
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