alu.fnsim.qmsg

设计带进位算术逻辑运算单元

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 15:17:05 2009 " "Info: Processing started: Mon Apr 20 15:17:05 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.v " "Warning: Can't analyze file -- file D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu181.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file alu181.v" { { "Info" "ISGN_ENTITY_NAME" "1 alu181 " "Info: Found entity 1: alu181" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt4.v" { { "Info" "ISGN_ENTITY_NAME" "1 cnt4 " "Info: Found entity 1: cnt4" {  } { { "cnt4.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/cnt4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "alu " "Info: Elaborating entity \"alu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu181 alu181:inst5 " "Info: Elaborating entity \"alu181\" for hierarchy \"alu181:inst5\"" {  } { { "alu.bdf" "inst5" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 40 376 496 168 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "M alu181.v(14) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(14): variable \"M\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 14 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(14) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(14): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 14 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "CN alu181.v(17) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(17): variable \"CN\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 17 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(17) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(17): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 17 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 alu181.v(17) " "Warning (10230): Verilog HDL assignment warning at alu181.v(17): truncated value with size 32 to match size of target (8)" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(18) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(18): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 18 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "M alu181.v(23) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(23): variable \"M\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 23 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(23) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(23): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 23 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "B alu181.v(23) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(23): variable \"B\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 23 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "CN alu181.v(26) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(26): variable \"CN\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 26 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(26) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(26): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 26 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "B alu181.v(26) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(26): variable \"B\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 26 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 alu181.v(26) " "Warning (10230): Verilog HDL assignment warning at alu181.v(26): truncated value with size 32 to match size of target (8)" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "A alu181.v(27) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(27): variable \"A\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 27 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "B alu181.v(27) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(27): variable \"B\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 27 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "M alu181.v(32) " "Warning (10235): Verilog HDL Always Construct warning at alu181.v(32): variable \"M\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 32 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}