alu.hier_info

设计带进位算术逻辑运算单元

|alu
co <= alu181:inst5.CO
cn => inst7.IN0
t4 => inst7.IN1
m => alu181:inst5.M
aclk => 74373b:inst1.G
IN[1] => 74373b:inst1.D[1]
IN[1] => 74373b:inst2.D[1]
IN[2] => 74373b:inst1.D[2]
IN[2] => 74373b:inst2.D[2]
IN[3] => 74373b:inst1.D[3]
IN[3] => 74373b:inst2.D[3]
IN[4] => 74373b:inst1.D[4]
IN[4] => 74373b:inst2.D[4]
IN[5] => 74373b:inst1.D[5]
IN[5] => 74373b:inst2.D[5]
IN[6] => 74373b:inst1.D[6]
IN[6] => 74373b:inst2.D[6]
IN[7] => 74373b:inst1.D[7]
IN[7] => 74373b:inst2.D[7]
IN[8] => 74373b:inst1.D[8]
IN[8] => 74373b:inst2.D[8]
bclk => 74373b:inst2.G
sclk => lpm_counter1:inst8.clock
A[0] <= 74373b:inst1.Q[1]
A[1] <= 74373b:inst1.Q[2]
A[2] <= 74373b:inst1.Q[3]
A[3] <= 74373b:inst1.Q[4]
A[4] <= 74373b:inst1.Q[5]
A[5] <= 74373b:inst1.Q[6]
A[6] <= 74373b:inst1.Q[7]
A[7] <= 74373b:inst1.Q[8]
B[0] <= 74373b:inst2.Q[1]
B[1] <= 74373b:inst2.Q[2]
B[2] <= 74373b:inst2.Q[3]
B[3] <= 74373b:inst2.Q[4]
B[4] <= 74373b:inst2.Q[5]
B[5] <= 74373b:inst2.Q[6]
B[6] <= 74373b:inst2.Q[7]
B[7] <= 74373b:inst2.Q[8]
F[0] <= alu181:inst5.F[0]
F[1] <= alu181:inst5.F[1]
F[2] <= alu181:inst5.F[2]
F[3] <= alu181:inst5.F[3]
F[4] <= alu181:inst5.F[4]
F[5] <= alu181:inst5.F[5]
F[6] <= alu181:inst5.F[6]
F[7] <= alu181:inst5.F[7]
S[0] <= lpm_counter1:inst8.q[0]
S[1] <= lpm_counter1:inst8.q[1]
S[2] <= lpm_counter1:inst8.q[2]
S[3] <= lpm_counter1:inst8.q[3]


|alu|alu181:inst5
A[0] => F~186.DATAB
A[0] => F~178.DATAA
A[0] => Add18.IN16
A[0] => Add17.IN16
A[0] => WideOr9.IN0
A[0] => Add15.IN16
A[0] => F~128.DATAA
A[0] => F~127.DATAB
A[0] => Add13.IN16
A[0] => Add9.IN8
A[0] => F~90.IN0
A[0] => Add7.IN16
A[0] => Add5.IN16
A[0] => WideOr1.IN0
A[0] => F~7.DATAA
A[0] => Add0.IN16
A[0] => WideNor0.IN0
A[0] => WideOr4.IN0
A[1] => F~185.DATAB
A[1] => F~177.DATAA
A[1] => Add18.IN15
A[1] => Add17.IN15
A[1] => WideOr9.IN7
A[1] => Add15.IN15
A[1] => F~126.DATAB
A[1] => Add13.IN14
A[1] => Add13.IN15
A[1] => Add9.IN7
A[1] => Add7.IN15
A[1] => Add5.IN15
A[1] => F~45.IN0
A[1] => WideOr1.IN6
A[1] => F~6.DATAA
A[1] => Add0.IN15
A[1] => WideNor0.IN7
A[1] => WideOr4.IN7
A[2] => F~184.DATAB
A[2] => F~176.DATAA
A[2] => Add18.IN14
A[2] => Add17.IN14
A[2] => WideOr9.IN6
A[2] => Add15.IN14
A[2] => F~125.DATAB
A[2] => Add13.IN12
A[2] => Add13.IN13
A[2] => Add9.IN6
A[2] => Add7.IN14
A[2] => Add5.IN14
A[2] => F~46.IN0
A[2] => WideOr1.IN5
A[2] => F~5.DATAA
A[2] => Add0.IN14
A[2] => WideNor0.IN6
A[2] => WideOr4.IN6
A[3] => F~183.DATAB
A[3] => F~175.DATAA
A[3] => Add18.IN13
A[3] => Add17.IN13
A[3] => WideOr9.IN5
A[3] => Add15.IN13
A[3] => F~124.DATAB
A[3] => Add13.IN10
A[3] => Add13.IN11
A[3] => Add9.IN5
A[3] => Add7.IN13
A[3] => Add5.IN13
A[3] => F~47.IN0
A[3] => WideOr1.IN4
A[3] => F~4.DATAA
A[3] => Add0.IN13
A[3] => WideNor0.IN5
A[3] => WideOr4.IN5
A[4] => F~182.DATAB
A[4] => F~174.DATAA
A[4] => Add18.IN12
A[4] => Add17.IN12
A[4] => WideOr9.IN4
A[4] => Add15.IN12
A[4] => F~123.DATAB
A[4] => Add13.IN8
A[4] => Add13.IN9
A[4] => Add9.IN4
A[4] => Add7.IN12
A[4] => Add5.IN12
A[4] => F~48.IN0
A[4] => WideOr1.IN3
A[4] => F~3.DATAA
A[4] => Add0.IN12
A[4] => WideNor0.IN4
A[4] => WideOr4.IN4
A[5] => F~181.DATAB
A[5] => F~173.DATAA
A[5] => Add18.IN11
A[5] => Add17.IN11
A[5] => WideOr9.IN3
A[5] => Add15.IN11
A[5] => F~122.DATAB
A[5] => Add13.IN6
A[5] => Add13.IN7
A[5] => Add9.IN3
A[5] => Add7.IN11
A[5] => Add5.IN11
A[5] => F~49.IN0
A[5] => WideOr1.IN2
A[5] => F~2.DATAA
A[5] => Add0.IN11
A[5] => WideNor0.IN3
A[5] => WideOr4.IN3
A[6] => F~180.DATAB
A[6] => F~172.DATAA
A[6] => Add18.IN10
A[6] => Add17.IN10
A[6] => WideOr9.IN2
A[6] => Add15.IN10
A[6] => F~121.DATAB
A[6] => Add13.IN4
A[6] => Add13.IN5
A[6] => Add9.IN2
A[6] => Add7.IN10
A[6] => Add5.IN10
A[6] => F~50.IN0
A[6] => WideOr1.IN1
A[6] => F~1.DATAA
A[6] => Add0.IN10
A[6] => WideNor0.IN2
A[6] => WideOr4.IN2
A[7] => F~179.DATAB
A[7] => F~171.DATAA
A[7] => Add18.IN9
A[7] => Add17.IN9
A[7] => WideOr9.IN1
A[7] => Add15.IN9
A[7] => Add13.IN2
A[7] => Add13.IN3
A[7] => Add9.IN1
A[7] => Add7.IN9
A[7] => Add5.IN9
A[7] => F~51.IN0
A[7] => F~0.DATAA
A[7] => Add0.IN9
A[7] => WideNor0.IN1
A[7] => WideOr4.IN1
B[0] => WideNor2.IN7
B[0] => WideOr8.IN7
B[0] => Add12.IN16
B[0] => F~117.DATAB
B[0] => Add9.IN16
B[0] => F~90.IN1
B[0] => WideOr3.IN7
B[0] => Add11.IN15
B[0] => Add5.IN8
B[1] => WideNor2.IN6
B[1] => WideOr8.IN6
B[1] => Add12.IN15
B[1] => F~116.DATAB
B[1] => Add9.IN15
B[1] => F~45.IN1
B[1] => WideOr3.IN6
B[1] => Add11.IN14
B[1] => Add5.IN7
B[2] => WideNor2.IN5
B[2] => WideOr8.IN5
B[2] => Add12.IN14
B[2] => F~115.DATAB
B[2] => Add9.IN14
B[2] => F~46.IN1
B[2] => WideOr3.IN5
B[2] => Add11.IN13
B[2] => Add5.IN6
B[3] => WideNor2.IN4
B[3] => WideOr8.IN4
B[3] => Add12.IN13
B[3] => F~114.DATAB
B[3] => Add9.IN13
B[3] => F~47.IN1
B[3] => WideOr3.IN4
B[3] => Add11.IN12
B[3] => Add5.IN5
B[4] => WideNor2.IN3
B[4] => WideOr8.IN3
B[4] => Add12.IN12
B[4] => F~113.DATAB
B[4] => Add9.IN12
B[4] => F~48.IN1
B[4] => WideOr3.IN3
B[4] => Add11.IN11
B[4] => Add5.IN4
B[5] => WideNor2.IN2
B[5] => WideOr8.IN2
B[5] => Add12.IN11
B[5] => F~112.DATAB
B[5] => Add9.IN11
B[5] => F~49.IN1
B[5] => WideOr3.IN2
B[5] => Add11.IN10
B[5] => Add5.IN3
B[6] => WideNor2.IN1
B[6] => WideOr8.IN1
B[6] => Add12.IN10
B[6] => F~111.DATAB
B[6] => Add9.IN10
B[6] => F~50.IN1
B[6] => WideOr3.IN1
B[6] => Add11.IN9
B[6] => Add5.IN2
B[7] => WideNor2.IN0
B[7] => WideOr8.IN0
B[7] => Add12.IN9
B[7] => F~110.DATAB
B[7] => Add9.IN9
B[7] => F~51.IN1
B[7] => WideOr3.IN0
B[7] => Add11.IN8
B[7] => Add5.IN1
S[0] => Mux7.IN19
S[0] => Mux6.IN19
S[0] => Mux5.IN19
S[0] => Mux4.IN19
S[0] => Mux3.IN19
S[0] => Mux2.IN19
S[0] => Mux1.IN19
S[0] => Mux0.IN19
S[1] => Mux7.IN18
S[1] => Mux6.IN18
S[1] => Mux5.IN18
S[1] => Mux4.IN18
S[1] => Mux3.IN18
S[1] => Mux2.IN18
S[1] => Mux1.IN18
S[1] => Mux0.IN18
S[2] => Mux7.IN17
S[2] => Mux6.IN17
S[2] => Mux5.IN17
S[2] => Mux4.IN17
S[2] => Mux3.IN17
S[2] => Mux2.IN17
S[2] => Mux1.IN17
S[2] => Mux0.IN17
S[3] => Mux7.IN16
S[3] => Mux6.IN16
S[3] => Mux5.IN16
S[3] => Mux4.IN16
S[3] => Mux3.IN16
S[3] => Mux2.IN16
S[3] => Mux1.IN16
S[3] => Mux0.IN16
CN => F~178.OUTPUTSELECT
CN => F~177.OUTPUTSELECT
CN => F~176.OUTPUTSELECT
CN => F~175.OUTPUTSELECT
CN => F~174.OUTPUTSELECT
CN => F~173.OUTPUTSELECT
CN => F~172.OUTPUTSELECT
CN => F~171.OUTPUTSELECT
CN => F~162.OUTPUTSELECT
CN => F~161.OUTPUTSELECT
CN => F~160.OUTPUTSELECT
CN => F~159.OUTPUTSELECT
CN => F~158.OUTPUTSELECT
CN => F~157.OUTPUTSELECT
CN => F~156.OUTPUTSELECT
CN => F~155.OUTPUTSELECT
CN => F~145.OUTPUTSELECT
CN => F~144.OUTPUTSELECT
CN => F~143.OUTPUTSELECT
CN => F~142.OUTPUTSELECT
CN => F~141.OUTPUTSELECT
CN => F~140.OUTPUTSELECT
CN => F~139.OUTPUTSELECT
CN => F~138.OUTPUTSELECT
CN => F~128.OUTPUTSELECT
CN => F~127.OUTPUTSELECT
CN => F~126.OUTPUTSELECT
CN => F~125.OUTPUTSELECT
CN => F~124.OUTPUTSELECT
CN => F~123.OUTPUTSELECT
CN => F~122.OUTPUTSELECT
CN => F~121.OUTPUTSELECT
CN => F~119.OUTPUTSELECT
CN => F~109.OUTPUTSELECT
CN => F~98.OUTPUTSELECT
CN => F~97.OUTPUTSELECT
CN => F~96.OUTPUTSELECT
CN => F~95.OUTPUTSELECT
CN => F~94.OUTPUTSELECT
CN => F~93.OUTPUTSELECT
CN => F~92.OUTPUTSELECT
CN => F~91.OUTPUTSELECT
CN => F~81.OUTPUTSELECT
CN => F~80.OUTPUTSELECT
CN => F~79.OUTPUTSELECT
CN => F~78.OUTPUTSELECT
CN => F~77.OUTPUTSELECT
CN => F~76.OUTPUTSELECT
CN => F~75.OUTPUTSELECT
CN => F~74.OUTPUTSELECT
CN => F~70.OUTPUTSELECT
CN => F~59.OUTPUTSELECT
CN => F~58.OUTPUTSELECT
CN => F~57.OUTPUTSELECT
CN => F~56.OUTPUTSELECT
CN => F~55.OUTPUTSELECT
CN => F~54.OUTPUTSELECT
CN => F~53.OUTPUTSELECT
CN => F~52.OUTPUTSELECT
CN => F~43.OUTPUTSELECT
CN => F~40.OUTPUTSELECT
CN => F~29.OUTPUTSELECT
CN => F~28.OUTPUTSELECT
CN => F~27.OUTPUTSELECT
CN => F~26.OUTPUTSELECT
CN => F~25.OUTPUTSELECT
CN => F~24.OUTPUTSELECT
CN => F~23.OUTPUTSELECT
CN => F~22.OUTPUTSELECT
CN => F~20.OUTPUTSELECT
CN => F~17.OUTPUTSELECT
CN => F~16.OUTPUTSELECT
CN => F~7.OUTPUTSELECT
CN => F~6.OUTPUTSELECT
CN => F~5.OUTPUTSELECT
CN => F~4.OUTPUTSELECT
CN => F~3.OUTPUTSELECT
CN => F~2.OUTPUTSELECT
CN => F~1.OUTPUTSELECT
CN => F~0.OUTPUTSELECT
CO <= <GND>
M => F~186.OUTPUTSELECT
M => F~185.OUTPUTSELECT
M => F~184.OUTPUTSELECT
M => F~183.OUTPUTSELECT
M => F~182.OUTPUTSELECT
M => F~181.OUTPUTSELECT
M => F~180.OUTPUTSELECT
M => F~179.OUTPUTSELECT
M => F~170.OUTPUTSELECT
M => F~169.OUTPUTSELECT
M => F~168.OUTPUTSELECT
M => F~167.OUTPUTSELECT
M => F~166.OUTPUTSELECT
M => F~165.OUTPUTSELECT
M => F~164.OUTPUTSELECT
M => F~163.OUTPUTSELECT
M => F~153.OUTPUTSELECT
M => F~152.OUTPUTSELECT
M => F~151.OUTPUTSELECT
M => F~150.OUTPUTSELECT
M => F~149.OUTPUTSELECT
M => F~148.OUTPUTSELECT
M => F~147.OUTPUTSELECT
M => F~146.OUTPUTSELECT
M => F~136.OUTPUTSELECT
M => F~135.OUTPUTSELECT
M => F~134.OUTPUTSELECT
M => F~133.OUTPUTSELECT
M => F~132.OUTPUTSELECT
M => F~131.OUTPUTSELECT
M => F~130.OUTPUTSELECT
M => F~129.OUTPUTSELECT
M => F~120.OUTPUTSELECT
M => F~117.OUTPUTSELECT
M => F~116.OUTPUTSELECT
M => F~115.OUTPUTSELECT
M => F~114.OUTPUTSELECT
M => F~113.OUTPUTSELECT
M => F~112.OUTPUTSELECT
M => F~111.OUTPUTSELECT
M => F~110.OUTPUTSELECT
M => F~106.OUTPUTSELECT
M => F~105.OUTPUTSELECT
M => F~104.OUTPUTSELECT
M => F~103.OUTPUTSELECT
M => F~102.OUTPUTSELECT
M => F~101.OUTPUTSELECT
M => F~100.OUTPUTSELECT
M => F~99.OUTPUTSELECT
M => F~89.OUTPUTSELECT
M => F~88.OUTPUTSELECT
M => F~87.OUTPUTSELECT
M => F~86.OUTPUTSELECT
M => F~85.OUTPUTSELECT
M => F~84.OUTPUTSELECT
M => F~83.OUTPUTSELECT
M => F~82.OUTPUTSELECT
M => F~71.OUTPUTSELECT
M => F~67.OUTPUTSELECT
M => F~66.OUTPUTSELECT
M => F~65.OUTPUTSELECT
M => F~64.OUTPUTSELECT
M => F~63.OUTPUTSELECT
M => F~62.OUTPUTSELECT
M => F~61.OUTPUTSELECT
M => F~60.OUTPUTSELECT
M => F~44.OUTPUTSELECT
M => F~41.OUTPUTSELECT
M => F~37.OUTPUTSELECT
M => F~36.OUTPUTSELECT
M => F~35.OUTPUTSELECT
M => F~34.OUTPUTSELECT
M => F~33.OUTPUTSELECT
M => F~32.OUTPUTSELECT
M => F~31.OUTPUTSELECT
M => F~30.OUTPUTSELECT
M => F~21.OUTPUTSELECT
M => F~19.OUTPUTSELECT
M => F~18.OUTPUTSELECT
M => F~15.OUTPUTSELECT
M => F~14.OUTPUTSELECT
M => F~13.OUTPUTSELECT
M => F~12.OUTPUTSELECT
M => F~11.OUTPUTSELECT
M => F~10.OUTPUTSELECT
M => F~9.OUTPUTSELECT
M => F~8.OUTPUTSELECT


|alu|74373b:inst1
Q8 <= 74.DB_MAX_OUTPUT_PORT_TYPE
D8 => 19.DATAIN
G => 19.LATCH_ENABLE
G => 18.LATCH_ENABLE
G => 17.LATCH_ENABLE
G => 16.LATCH_ENABLE
G => 15.LATCH_ENABLE
G => 14.LATCH_ENABLE
G => 13.LATCH_ENABLE
G => 12.LATCH_ENABLE
OEN => 1.IN0
Q7 <= 73.DB_MAX_OUTPUT_PORT_TYPE
D7 => 18.DATAIN
Q6 <= 72.DB_MAX_OUTPUT_PORT_TYPE
D6 => 17.DATAIN
Q5 <= 71.DB_MAX_OUTPUT_PORT_TYPE
D5 => 16.DATAIN
Q4 <= 70.DB_MAX_OUTPUT_PORT_TYPE
D4 => 15.DATAIN
Q3 <= 69.DB_MAX_OUTPUT_PORT_TYPE
D3 => 14.DATAIN
Q2 <= 68.DB_MAX_OUTPUT_PORT_TYPE
D2 => 13.DATAIN
Q1 <= 67.DB_MAX_OUTPUT_PORT_TYPE
D1 => 12.DATAIN


|alu|74373b:inst2
Q8 <= 74.DB_MAX_OUTPUT_PORT_TYPE
D8 => 19.DATAIN
G => 19.LATCH_ENABLE
G => 18.LATCH_ENABLE
G => 17.LATCH_ENABLE
G => 16.LATCH_ENABLE
G => 15.LATCH_ENABLE
G => 14.LATCH_ENABLE
G => 13.LATCH_ENABLE
G => 12.LATCH_ENABLE
OEN => 1.IN0
Q7 <= 73.DB_MAX_OUTPUT_PORT_TYPE
D7 => 18.DATAIN
Q6 <= 72.DB_MAX_OUTPUT_PORT_TYPE
D6 => 17.DATAIN
Q5 <= 71.DB_MAX_OUTPUT_PORT_TYPE
D5 => 16.DATAIN
Q4 <= 70.DB_MAX_OUTPUT_PORT_TYPE
D4 => 15.DATAIN
Q3 <= 69.DB_MAX_OUTPUT_PORT_TYPE
D3 => 14.DATAIN
Q2 <= 68.DB_MAX_OUTPUT_PORT_TYPE
D2 => 13.DATAIN
Q1 <= 67.DB_MAX_OUTPUT_PORT_TYPE
D1 => 12.DATAIN


|alu|lpm_counter1:inst8
clock => clock~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q


|alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component
clock => cntr_6dh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_6dh:auto_generated.q[0]
q[1] <= cntr_6dh:auto_generated.q[1]
q[2] <= cntr_6dh:auto_generated.q[2]
q[3] <= cntr_6dh:auto_generated.q[3]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT