prev_cmp_alu.tan.qmsg

来自「设计带进位算术逻辑运算单元」· QMSG 代码 · 共 16 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sclk " "Info: Assuming node \"sclk\" is an undefined clock" {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "a0_b1 " "Info: Assuming node \"a0_b1\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "a0_b1" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sclk register register lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 275.03 MHz Internal " "Info: Clock \"sclk\" Internal fmax is restricted to 275.03 MHz between source register \"lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]\" and destination register \"lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.034 ns + Longest register register " "Info: + Longest register to register delay is 2.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] 1 REG LC_X12_Y17_N6 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y17_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.592 ns) + CELL(0.575 ns) 1.167 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X12_Y17_N6 2 " "Info: 2: + IC(0.592 ns) + CELL(0.575 ns) = 1.167 ns; Loc. = LC_X12_Y17_N6; Fanout = 2; COMB Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.247 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella2~COUTCOUT1 3 COMB LC_X12_Y17_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.247 ns; Loc. = LC_X12_Y17_N7; Fanout = 1; COMB Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.034 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 4 REG LC_X12_Y17_N8 25 " "Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.034 ns; Loc. = LC_X12_Y17_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.787 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns ( 70.89 % ) " "Info: Total cell delay = 1.442 ns ( 70.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.592 ns ( 29.11 % ) " "Info: Total interconnect delay = 0.592 ns ( 29.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.034 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.034 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.592ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.246 ns + Shortest register " "Info: + Shortest clock path from clock \"sclk\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'sclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 2 REG LC_X12_Y17_N8 25 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X12_Y17_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.246 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; CLK Node = 'sclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] 2 REG LC_X12_Y17_N6 35 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X12_Y17_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.034 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.034 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.592ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } {  } {  } "" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "74373b:inst1\|14 IN\[3\] a0_b1 6.531 ns register " "Info: tsu for register \"74373b:inst1\|14\" (data pin = \"IN\[3\]\", clock pin = \"a0_b1\") is 6.531 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.871 ns + Longest pin register " "Info: + Longest pin to register delay is 8.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns IN\[3\] 1 PIN PIN_41 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_41; Fanout = 2; PIN Node = 'IN\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { IN[3] } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 80 -256 -88 96 "IN\[8..1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.960 ns) + CELL(0.442 ns) 8.871 ns 74373b:inst1\|14 2 REG LC_X13_Y17_N2 28 " "Info: 2: + IC(6.960 ns) + CELL(0.442 ns) = 8.871 ns; Loc. = LC_X13_Y17_N2; Fanout = 28; REG Node = '74373b:inst1\|14'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "7.402 ns" { IN[3] 74373b:inst1|14 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 21.54 % ) " "Info: Total cell delay = 1.911 ns ( 21.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.960 ns ( 78.46 % ) " "Info: Total interconnect delay = 6.960 ns ( 78.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.871 ns" { IN[3] 74373b:inst1|14 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.871 ns" { IN[3] {} IN[3]~out0 {} 74373b:inst1|14 {} } { 0.000ns 0.000ns 6.960ns } { 0.000ns 1.469ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.872 ns + " "Info: + Micro setup delay of destination is 0.872 ns" {  } { { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a0_b1 destination 3.212 ns - Shortest register " "Info: - Shortest clock path from clock \"a0_b1\" to destination register is 3.212 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns a0_b1 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'a0_b1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0_b1 } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "a0_b1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.629 ns) + CELL(0.114 ns) 3.212 ns 74373b:inst1\|14 2 REG LC_X13_Y17_N2 28 " "Info: 2: + IC(1.629 ns) + CELL(0.114 ns) = 3.212 ns; Loc. = LC_X13_Y17_N2; Fanout = 28; REG Node = '74373b:inst1\|14'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.743 ns" { a0_b1 74373b:inst1|14 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 49.28 % ) " "Info: Total cell delay = 1.583 ns ( 49.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.629 ns ( 50.72 % ) " "Info: Total interconnect delay = 1.629 ns ( 50.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { a0_b1 74373b:inst1|14 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { a0_b1 {} a0_b1~out0 {} 74373b:inst1|14 {} } { 0.000ns 0.000ns 1.629ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.871 ns" { IN[3] 74373b:inst1|14 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.871 ns" { IN[3] {} IN[3]~out0 {} 74373b:inst1|14 {} } { 0.000ns 0.000ns 6.960ns } { 0.000ns 1.469ns 0.442ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.212 ns" { a0_b1 74373b:inst1|14 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.212 ns" { a0_b1 {} a0_b1~out0 {} 74373b:inst1|14 {} } { 0.000ns 0.000ns 1.629ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "a0_b1 F\[7\] 74373b:inst2\|12 76.139 ns register " "Info: tco from clock \"a0_b1\" to destination pin \"F\[7\]\" through register \"74373b:inst2\|12\" is 76.139 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a0_b1 source 3.201 ns + Longest register " "Info: + Longest clock path from clock \"a0_b1\" to source register is 3.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns a0_b1 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'a0_b1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { a0_b1 } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "a0_b1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.618 ns) + CELL(0.114 ns) 3.201 ns 74373b:inst2\|12 2 REG LC_X13_Y16_N8 13 " "Info: 2: + IC(1.618 ns) + CELL(0.114 ns) = 3.201 ns; Loc. = LC_X13_Y16_N8; Fanout = 13; REG Node = '74373b:inst2\|12'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.732 ns" { a0_b1 74373b:inst2|12 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 49.45 % ) " "Info: Total cell delay = 1.583 ns ( 49.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.618 ns ( 50.55 % ) " "Info: Total interconnect delay = 1.618 ns ( 50.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.201 ns" { a0_b1 74373b:inst2|12 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.201 ns" { a0_b1 {} a0_b1~out0 {} 74373b:inst2|12 {} } { 0.000ns 0.000ns 1.618ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "72.938 ns + Longest register pin " "Info: + Longest register to pin delay is 72.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74373b:inst2\|12 1 REG LC_X13_Y16_N8 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y16_N8; Fanout = 13; REG Node = '74373b:inst2\|12'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74373b:inst2|12 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.074 ns) + CELL(0.114 ns) 2.188 ns alu181:inst5\|WideOr8~69 2 COMB LC_X14_Y16_N4 1 " "Info: 2: + IC(2.074 ns) + CELL(0.114 ns) = 2.188 ns; Loc. = LC_X14_Y16_N4; Fanout = 1; COMB Node = 'alu181:inst5\|WideOr8~69'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.188 ns" { 74373b:inst2|12 alu181:inst5|WideOr8~69 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.442 ns) 3.869 ns alu181:inst5\|WideOr8 3 COMB LC_X14_Y19_N3 11 " "Info: 3: + IC(1.239 ns) + CELL(0.442 ns) = 3.869 ns; Loc. = LC_X14_Y19_N3; Fanout = 11; COMB Node = 'alu181:inst5\|WideOr8'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { alu181:inst5|WideOr8~69 alu181:inst5|WideOr8 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.292 ns) 6.269 ns alu181:inst5\|F~137 4 COMB LC_X16_Y17_N9 3 " "Info: 4: + IC(2.108 ns) + CELL(0.292 ns) = 6.269 ns; Loc. = LC_X16_Y17_N9; Fanout = 3; COMB Node = 'alu181:inst5\|F~137'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { alu181:inst5|WideOr8 alu181:inst5|F~137 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.423 ns) 7.362 ns alu181:inst5\|Add15~116 5 COMB LC_X15_Y17_N0 2 " "Info: 5: + IC(0.670 ns) + CELL(0.423 ns) = 7.362 ns; Loc. = LC_X15_Y17_N0; Fanout = 2; COMB Node = 'alu181:inst5\|Add15~116'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.093 ns" { alu181:inst5|F~137 alu181:inst5|Add15~116 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.440 ns alu181:inst5\|Add15~114 6 COMB LC_X15_Y17_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 7.440 ns; Loc. = LC_X15_Y17_N1; Fanout = 2; COMB Node = 'alu181:inst5\|Add15~114'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { alu181:inst5|Add15~116 alu181:inst5|Add15~114 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.518 ns alu181:inst5\|Add15~112 7 COMB LC_X15_Y17_N2 2 " "Info: 7: + IC(0.000 ns) + CELL(0.078 ns) = 7.518 ns; Loc. = LC_X15_Y17_N2; Fanout = 2; COMB Node = 'alu181:inst5\|Add15~112'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { alu181:inst5|Add15~114 alu181:inst5|Add15~112 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 7.596 ns alu181:inst5\|Add15~110 8 COMB LC_X15_Y17_N3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.078 ns) = 7.596 ns; Loc. = LC_X15_Y17_N3; Fanout = 2; COMB Node = 'alu181:inst5\|Add15~110'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { alu181:inst5|Add15~112 alu181:inst5|Add15~110 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 7.774 ns alu181:inst5\|Add15~108 9 COMB LC_X15_Y17_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.178 ns) = 7.774 ns; Loc. = LC_X15_Y17_N4; Fanout = 3; COMB Node = 'alu181:inst5\|Add15~108'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { alu181:inst5|Add15~110 alu181:inst5|Add15~108 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 8.395 ns alu181:inst5\|Add15~103 10 COMB LC_X15_Y17_N6 3 " "Info: 10: + IC(0.000 ns) + CELL(0.621 ns) = 8.395 ns; Loc. = LC_X15_Y17_N6; Fanout = 3; COMB Node = 'alu181:inst5\|Add15~103'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { alu181:inst5|Add15~108 alu181:inst5|Add15~103 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.590 ns) 9.414 ns alu181:inst5\|F~1365 11 COMB LC_X15_Y17_N8 1 " "Info: 11: + IC(0.429 ns) + CELL(0.590 ns) = 9.414 ns; Loc. = LC_X15_Y17_N8; Fanout = 1; COMB Node = 'alu181:inst5\|F~1365'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.019 ns" { alu181:inst5|Add15~103 alu181:inst5|F~1365 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.590 ns) 11.230 ns alu181:inst5\|F~1367 12 COMB LC_X16_Y16_N4 1 " "Info: 12: + IC(1.226 ns) + CELL(0.590 ns) = 11.230 ns; Loc. = LC_X16_Y16_N4; Fanout = 1; COMB Node = 'alu181:inst5\|F~1367'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.816 ns" { alu181:inst5|F~1365 alu181:inst5|F~1367 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.292 ns) 12.761 ns alu181:inst5\|Mux7~140 13 COMB LC_X16_Y18_N7 1 " "Info: 13: + IC(1.239 ns) + CELL(0.292 ns) = 12.761 ns; Loc. = LC_X16_Y18_N7; Fanout = 1; COMB Node = 'alu181:inst5\|Mux7~140'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.531 ns" { alu181:inst5|F~1367 alu181:inst5|Mux7~140 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.292 ns) 13.498 ns alu181:inst5\|Mux7~141 14 COMB LC_X16_Y18_N6 1 " "Info: 14: + IC(0.445 ns) + CELL(0.292 ns) = 13.498 ns; Loc. = LC_X16_Y18_N6; Fanout = 1; COMB Node = 'alu181:inst5\|Mux7~141'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.737 ns" { alu181:inst5|Mux7~140 alu181:inst5|Mux7~141 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.114 ns) 14.041 ns alu181:inst5\|Mux7~144 15 COMB LC_X16_Y18_N0 2 " "Info: 15: + IC(0.429 ns) + CELL(0.114 ns) = 14.041 ns; Loc. = LC_X16_Y18_N0; Fanout = 2; COMB Node = 'alu181:inst5\|Mux7~144'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.543 ns" { alu181:inst5|Mux7~141 alu181:inst5|Mux7~144 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.849 ns) 14.890 ns alu181:inst5\|Mux7~147 16 COMB LOOP LC_X16_Y18_N4 4 " "Info: 16: + IC(0.000 ns) + CELL(0.849 ns) = 14.890 ns; Loc. = LC_X16_Y18_N4; Fanout = 4; COMB LOOP Node = 'alu181:inst5\|Mux7~147'" { { "Info" "ITDB_PART_OF_SCC" "a