uart.vhd

依元素开发板的示例程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity uart is
    Port (clk,reset:in std_logic;
	       txflag : in std_logic;
	       a:        out std_logic_vector(3 downto 0);
			 l:        out std_logic_vector(6 downto 0);
			 RxD:      in std_logic;
			 TxD:      out std_logic
			 );
end uart;

architecture Behavioral of uart is

  component Counter is
  generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
  port (
     Clk      : in  Std_Logic;  -- Clock
     Reset    : in  Std_Logic;  -- Reset input
     CE       : in  Std_Logic;  -- Chip Enable
     O        : out Std_Logic); -- Output  
  end component;

  component RxUnit is
  port (
     Clk    : in  Std_Logic;  -- system clock signal
     Reset  : in  Std_Logic;  -- Reset input
     Enable : in  Std_Logic;  -- Enable input
     RxD    : in  Std_Logic;  -- RS-232 data input
     RxAv   : out Std_Logic;  -- Byte available
     In_Data: out Std_Logic_Vector(7 downto 0)); -- Byte received
  end component;

  component txunit is
    Port ( clk : in std_logic;
           reset : in std_logic;
           enable : in std_logic; --enable ouput
			  txflag : in std_logic;  --enable one send byte
           datain : in std_logic_vector(7 downto 0); -- byte to be sent
           TxD : out std_logic);--out data
  end component;

  component lcd is
  port(
         clk:in std_logic;
	      sw:in std_logic_vector(7 downto 0);
	      l :out std_logic_vector(6 downto 0);
		   a :out std_logic_vector(3 downto 0)		
   	 );
  end component;

   component BUFGP
         port (I: in std_logic; O: out std_logic);
   end component; 

  signal RxAv   : Std_Logic;
  signal rxdata : std_logic;
  signal Enable : Std_Logic;
  signal In_data,q: std_logic_vector(7 downto 0);
  signal s1,s2  :std_logic;

  --signal txflag : std_logic;  --enable one send byte
  signal datain : std_logic_vector(7 downto 0); -- byte to be sent

  signal lcdcnt : std_logic_vector(6 downto 0);
  signal lcdclk : std_logic;

begin
  
  process (reset,Enable)--make the led show clock
  begin
    if reset='0' then
	   lcdcnt <= (others=>'0');
	 elsif (Enable'event and Enable='1') then
	   lcdcnt <= lcdcnt + 1;
	 end if;
  end process;

  lcdclk <= lcdcnt(6);
  --txflag <= '1';
  datain <= "01010101";

  --s1<='0';
  s2<='1'; 
  U2:  BUFGP port map (I => RxD, O => rxdata);

  Uart_Rxrate : Counter 
     generic map (COUNT => 108)--BRDIVISOR) 
     port map (clk, reset, s2, Enable);
 
  Uart_RxUnit : RxUnit 
     port map (clk, reset, Enable, rxdata, RxAv, In_data);

  Uart_TxDUnit : txunit 
    Port map ( clk, reset, Enable, txflag, datain, TxD);

  u1:lcd port map(lcdclk,q,l,a);

  process(clk,reset)
  begin
    if reset='0' then
	   q<="00000000";
	 elsif clk'event and clk='1' then
	   if RxAv='1' then
		  q<=In_data;
		end if;
	 end if;
  end process;

end Behavioral;