txunit.vhd

来自「依元素开发板的示例程序」· VHDL 代码 · 共 76 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity txunit is
    Port ( clk : in std_logic;
           reset : in std_logic;
           enable : in std_logic;
			  txflag : in std_logic;
           datain : in std_logic_vector(7 downto 0);
           TxD : out std_logic);
end txunit;

architecture Behavioral of txunit is
  signal TReg    : Std_Logic_Vector(7 downto 0); -- receive register  
  --signal RRegL   : Std_Logic;                    -- Byte received
begin

  TReg <= datain;  

  -- Rx Process
  RxProc : process(clk,reset,enable,TReg)
  variable BitPos : INTEGER range 0 to 11;   -- Position of the bit in the frame
  variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit 
  begin
     if reset = '0' then -- Reset
        BitPos := 0;           
     elsif Rising_Edge(clk) then
        if enable = '1' then
           case BitPos is
              when 0 => -- idle
                 if txflag = '0' then -- Start Bit
					     TxD <= '0';  
                    SampleCnt := 0;
					     BitPos := 1;
                 end if;
				  when 1 =>
				     TxD <= '0';  --send the start bit
					  if SampleCnt = 3 then -- Increment BitPos on 3
                    BitPos := BitPos + 1;
                 end if;
              when 11 => -- Stop Bit
                 TxD <= '1';  -- Store received byte
					  if SampleCnt = 3 then -- Increment BitPos on 3
                    BitPos := 0;
                 end if;
				  when 10 =>
                 if SampleCnt = 1 then -- Sample RxD on 1
                    TxD <= '1'; -- Deserialisation
                 end if;
                 if SampleCnt = 3 then -- Increment BitPos on 3
                    BitPos := 11;
                 end if;
              when others =>
                 if SampleCnt = 1 then -- Sample RxD on 1
                    TxD <= TReg(BitPos-2); -- Deserialisation
                 end if;
                 if SampleCnt = 3 then -- Increment BitPos on 3
                    BitPos := BitPos + 1;
                 end if;
           end case;
           if SampleCnt = 3 then -- Optionaly (SampleCnt can be free running)
              SampleCnt := 0;
           else   
              sampleCnt := SampleCnt + 1;
           end if;
           
        end if;
     end if;
  end process;



end Behavioral;