cntr4.v

来自「脉冲宽度调试机器程序设计 具体请看英文描述」· Verilog 代码 · 共 16 行

`timescale 1ns / 1ps
//4-bit binary up counter
module cntr4(input clock, 
				input reset, 
				output reg [3:0] count);

always @(posedge clock or posedge reset)
begin
	if (reset == 1'b1)  //asynchronous reset
		count <= 4'b0;
	else
		count <= count + 1;	
end

endmodule