mag4comp.v

来自「脉冲宽度调试机器程序设计 具体请看英文描述」· Verilog 代码 · 共 17 行

`timescale 1ns / 1ps
//4-bit magnetude comparator
module mag4comp(input [3:0] a,  //inputs to compare
					input [3:0] b, 
					input aeqbin, 	  //expansion inputs
					input agtbin, 
					input altbin, 
					output aeqbout,  //outputs
					output agtbout, 
					output altbout);

assign aeqbout = ((a == b)&&(aeqbin == 1'b1))? 1'b1 : 1'b0;
assign agtbout = ((a > b)||((a == b)&&(agtbin == 1'b1)))? 1 : 0;
assign altbout = (a < b)|((a == b) & altbin);

endmodule