__projnav.log

脉冲宽度调试机器程序设计 具体请看英文描述

Project Navigator Auto-Make Log File
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Started process "Check Syntax for Simulation".

Compiling project file "mag4comp_stx.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/mag4comp.v"
Module <mag4comp> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/mag4comp.v: 0.13
Compiling verilog file "C:/Xilinx/verilog/src/glbl.v"
Module <glbl> compiled
Parsing C:/Xilinx/verilog/src/glbl.v: 0.08


Project Navigator Auto-Make Log File
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Started process "Check Syntax for Simulation".

Compiling project file "mag4comp_stx.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/mag4comp.v"
ERROR:HDLCompilers:28 - "U:\pdrive_labs\en518_2007\PWM/mag4comp.v" line 14 'altbin' has not been declared
Module <mag4comp> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/mag4comp.v: 0.01
ERROR: vlogcomp failed
Process "Check Syntax for Simulation" did not complete.


Project Navigator Auto-Make Log File
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Started process "Check Syntax for Simulation".

Compiling project file "mag4comp_stx.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/mag4comp.v"
Module <mag4comp> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/mag4comp.v: 0.06
Compiling verilog file "C:/Xilinx/verilog/src/glbl.v"
Module <glbl> compiled
Parsing C:/Xilinx/verilog/src/glbl.v: 0.05


Project Navigator Auto-Make Log File
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Compiling verilog file "mag4comp.v"
tdtfi(verilog) completed successfully.



Project Navigator Auto-Make Log File
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Started process "Check Syntax".

Compiling project file "test_mag4comp_v_stx.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/mag4comp.v"
Module <mag4comp> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/mag4comp.v: 0.09
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_mag4comp.v"
Module <test_mag4comp_v> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_mag4comp.v: 0.06
Compiling verilog file "C:/Xilinx/verilog/src/glbl.v"
Module <glbl> compiled
Parsing C:/Xilinx/verilog/src/glbl.v: 0.06


Project Navigator Auto-Make Log File
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Compiling project file "test_mag4comp_v_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/mag4comp.v"
Module <mag4comp> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/mag4comp.v: 0.13
Codegen work/mag4comp: 1.41
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_mag4comp.v"
Module <test_mag4comp_v> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_mag4comp.v: 0.08
Codegen work/test_mag4comp_v: 0.44
Compiling verilog file "C:/Xilinx/verilog/src/glbl.v"
Module <glbl> compiled
Parsing C:/Xilinx/verilog/src/glbl.v: 0.06
Codegen work/glbl: 0.78
Building test_mag4comp_v_isim_beh.exe


Project Navigator Auto-Make Log File
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Started process "Check Syntax for Simulation".

Compiling project file "cntr4_stx.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/cntr4.v"
Module <cntr4> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/cntr4.v: 0.11
Compiling verilog file "C:/Xilinx/verilog/src/glbl.v"
Module <glbl> compiled
Parsing C:/Xilinx/verilog/src/glbl.v: 0.08


Project Navigator Auto-Make Log File
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Compiling project file "test_cntr4_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/cntr4.v"
Module <cntr4> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/cntr4.v: 0.08
Codegen work/cntr4: 0.52
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_cntr4.tfw"
Module <test_cntr4> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_cntr4.tfw: 0.05
Codegen work/test_cntr4: 0.64
Building test_cntr4_isim_beh.exe


Project Navigator Auto-Make Log File
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Compiling project file "test_cntr4_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_cntr4.tfw"
Module <test_cntr4> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_cntr4.tfw: 0.09
Codegen work/test_cntr4: 0.63
Building test_cntr4_isim_beh.exe


Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling verilog file "cntr4.v"
tdtfi(verilog) completed successfully.






Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling verilog file "mag4comp.v"
tdtfi(verilog) completed successfully.






Project Navigator Auto-Make Log File
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Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Verilog netlist file generated.


Project Navigator Auto-Make Log File
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Compiling project file "test_pwm_sch_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/pwm_sch.vf"
Module <pwm_sch> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/pwm_sch.vf: 0.09
Codegen work/pwm_sch: 0.55
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw"
Module <test_pwm_sch> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw: 0.08
Codegen work/test_pwm_sch: 0.64
Codegen uni9000_ver/GND: 0.36
Codegen uni9000_ver/OR2: 0.39
Codegen uni9000_ver/VCC: 0.34
Building test_pwm_sch_isim_beh.exe


Project Navigator Auto-Make Log File
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Compiling project file "test_pwm_sch_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw"
Module <test_pwm_sch> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw: 0.08
Codegen work/test_pwm_sch: 0.77
Building test_pwm_sch_isim_beh.exe


Project Navigator Auto-Make Log File
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Compiling project file "test_pwm_sch_beh.prj"
Compiling verilog file "U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw"
Module <test_pwm_sch> compiled
Parsing U:\pdrive_labs\en518_2007\PWM/test_pwm_sch.tfw: 0.08
Codegen work/test_pwm_sch: 0.72
Building test_pwm_sch_isim_beh.exe