test_cntr4.tbw

脉冲宽度调试机器程序设计 具体请看英文描述

version 3
u:\pdrive_labs\en518_2007\pwm\cntr4.v
cntr4
VERILOG
VERILOG
test_cntr4.xwv
Clocked
-
-
5000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
count
clock
reset
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
count_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
reset
count
SIGNAL_ORDER_END
-X-X-X-