📄 test_pwm_sch.tfw
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1.04i
// \ \ Application : ISE Foundation
// / / Filename : test_pwm_sch.tfw
// /___/ /\ Timestamp : Wed Feb 21 16:11:55 2007
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name: test_pwm_sch
//Device: Xilinx
//
`timescale 1ns/1ps
module test_pwm_sch;
reg CLK = 1'b0;
reg [3:0] DATA = 4'b0000;
reg RST = 1'b1;
wire PWM;
parameter PERIOD = 200;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for CLK
begin
#OFFSET;
forever
begin
CLK = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
pwm_sch UUT (
.CLK(CLK),
.DATA(DATA),
.RST(RST),
.PWM(PWM));
integer TX_FILE = 0;
integer TX_ERROR = 0;
initial begin // Open the results file...
TX_FILE = $fopen("results.txt");
#100200 // Final time: 100200 ns
if (TX_ERROR == 0) begin
$display("No errors or warnings.");
$fdisplay(TX_FILE, "No errors or warnings.");
end else begin
$display("%d errors found in simulation.", TX_ERROR);
$fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
end
$fclose(TX_FILE);
$stop;
end
initial begin
// ------------- Current Time: 285ns
#285;
RST = 1'b0;
// -------------------------------------
end
task CHECK_PWM;
input NEXT_PWM;
#0 begin
if (NEXT_PWM !== PWM) begin
$display("Error at time=%dns PWM=%b, expected=%b", $time, PWM, NEXT_PWM);
$fdisplay(TX_FILE, "Error at time=%dns PWM=%b, expected=%b", $time, PWM, NEXT_PWM);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
end
endtask
endmodule
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