test_mag4comp.v

来自「脉冲宽度调试机器程序设计 具体请看英文描述」· Verilog 代码 · 共 62 行

`timescale 1ns / 1ps

module test_mag4comp_v;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;
	reg aeqbin;
	reg agtbin;
	reg altbin;

	// Outputs
	wire aeqbout;
	wire agtbout;
	wire altbout;

	// Instantiate the Unit Under Test (UUT)
	mag4comp uut (
		.a(a), 
		.b(b), 
		.aeqbin(aeqbin), 
		.agtbin(agtbin), 
		.altbin(altbin), 
		.aeqbout(aeqbout), 
		.agtbout(agtbout), 
		.altbout(altbout)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
		aeqbin = 0;
		agtbin = 0;
		altbin = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		aeqbin = 1'b1;
		#100;
		a = 4'b1100;
		#100;
		b = 4'b1101;
		#100;
		a = 4'b1001;
		#100;
		b = 4'b1001;
		#100;
		agtbin = 1'b1;
		aeqbin = 1'b0;
		#100;
		agtbin = 1'b0;
		altbin = 1'b1;
		#100;
		$stop;
	end
      
endmodule