pwm_sch.vf

脉冲宽度调试机器程序设计 具体请看英文描述

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.04i
//  \   \         Application : sch2verilog
//  /   /         Filename : pwm_sch.vf
// /___/   /\     Timestamp : 02/21/2007 15:49:44
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: C:/Xilinx/bin/nt/sch2verilog.exe -intstyle ise -family xc9500 -w pwm_sch.sch pwm_sch.vf
//Design Name: pwm_sch
//Device: xc9500
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module pwm_sch(CLK, 
               DATA, 
               RST, 
               PWM);

    input CLK;
    input [3:0] DATA;
    input RST;
   output PWM;
   
   wire [3:0] C;
   wire XLXN_1;
   wire XLXN_3;
   wire XLXN_8;
   wire XLXN_9;
   
   cntr4 XLXI_1 (.clock(CLK), 
                 .reset(RST), 
                 .count(C[3:0]));
   mag4comp XLXI_2 (.a(C[3:0]), 
                    .aeqbin(XLXN_1), 
                    .agtbin(XLXN_3), 
                    .altbin(XLXN_3), 
                    .b(DATA[3:0]), 
                    .aeqbout(XLXN_8), 
                    .agtbout(XLXN_9), 
                    .altbout());
   OR2 XLXI_3 (.I0(XLXN_9), 
               .I1(XLXN_8), 
               .O(PWM));
   GND XLXI_4 (.G(XLXN_3));
   VCC XLXI_5 (.P(XLXN_1));
endmodule