xsimtest__pwm__sch.cpp

脉冲宽度调试机器程序设计 具体请看英文描述

#include "work/test__pwm__sch/test__pwm__sch.h"
#include "work/glbl/glbl.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";


#include "work/test__pwm__sch/test__pwm__sch.h"
static HSim__s6* IF0(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMtest__pwm__sch(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_g_n_d/_g_n_d.h"
static HSim__s6* IF1(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_g_n_d(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_o_r2/_o_r2.h"
static HSim__s6* IF2(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_o_r2(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_v_c_c/_v_c_c.h"
static HSim__s6* IF3(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_v_c_c(label); 
    return blk;
}


#include "work/mag4comp/mag4comp.h"
static HSim__s6* IF4(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMmag4comp(label); 
    return blk;
}


#include "work/cntr4/cntr4.h"
static HSim__s6* IF5(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMcntr4(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_v_c_c/_v_c_c.h"
static HSim__s6* IF6(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_v_c_c(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_o_r2/_o_r2.h"
static HSim__s6* IF7(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_o_r2(label); 
    return blk;
}


#include "uni9000_ver.auxlib/_g_n_d/_g_n_d.h"
static HSim__s6* IF8(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new uni9000_ver_auxlibM_g_n_d(label); 
    return blk;
}


#include "work/pwm__sch/pwm__sch.h"
static HSim__s6* IF9(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMpwm__sch(label); 
    return blk;
}


#include "work/glbl/glbl.h"
static HSim__s6* IF10(HSim__s6 * Arch,
const char* label, 
int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMglbl(label); 
    return blk;
}

class _top : public HSim__s5 {
public:
    _top() : HSim__s5("_top", "_top", 0) {}
    void moduleInstantiate (HSimConfigDecl * cfg) {
        HSim__s5 * topvl = 0;
        topvl = new workMtest__pwm__sch("test_pwm_sch");
        topvl->moduleInstantiate(cfg);
         addChild(topvl);
        topvl = new workMglbl("glbl");
        topvl->moduleInstantiate(cfg);
         addChild(topvl);
}
    void setDefparam() {}
    void constructObject() {}
    void connectSigs() {}    void archImplement() {}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s5 * _top_i = 0;
  try {
    HSimConfigDecl cfg(" default ");
    cfg.addVlogModule("test_pwm_sch", (HSimInstFactoryPtr)IF0);
    cfg.addVlogModule("GND", (HSimInstFactoryPtr)IF1);
    cfg.addVlogModule("OR2", (HSimInstFactoryPtr)IF2);
    cfg.addVlogModule("VCC", (HSimInstFactoryPtr)IF3);
    cfg.addVlogModule("mag4comp", (HSimInstFactoryPtr)IF4);
    cfg.addVlogModule("cntr4", (HSimInstFactoryPtr)IF5);
    cfg.addVlogModule("VCC", (HSimInstFactoryPtr)IF6);
    cfg.addVlogModule("OR2", (HSimInstFactoryPtr)IF7);
    cfg.addVlogModule("GND", (HSimInstFactoryPtr)IF8);
    cfg.addVlogModule("pwm_sch", (HSimInstFactoryPtr)IF9);
    cfg.addVlogModule("glbl", (HSimInstFactoryPtr)IF10);
 _top_i = new _top();
  _top_i->moduleInstantiate(&cfg);
    return globalKernel->runTcl(&cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}