edgedet.vhd

来自「海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity edgedet is
	port(detected : out std_logic;
			edge_in, clock, reset : in std_logic);
end edgedet;

architecture v1 of edgedet is
	signal q0, q1 : std_logic;
begin

	dff0 : entity work.dff(v1)
		port map(q => q0, d => edge_in, clk => clock, reset => reset);
	dff1 : entity work.dff(v1)
		port map(q => q1, d => q0, clk => clock, reset => reset);
		
	--changed due to reset problem	 
	--was: detected <= q0 and not q1;
	detected <= not q0 and q1;

end v1;