dff.vhd

来自「海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述」· VHDL 代码 · 共 19 行

--d-type flip-flop with asynch reset
library ieee;
use ieee.std_logic_1164.all;
entity dff is
	port(q : out std_logic;
			d, clk, reset : in std_logic);
end dff;

architecture v1 of dff is
begin
	process(clk, reset)
	begin
		if reset = '1' then
			q <= '0';
		elsif rising_edge(clk) then
			q <= d;	 
		end if;
	end process;
end v1;