timer.vhd

来自「海尔布伦 访问状态机 设计 用FSM方式 verilog HDL 语言描述」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Timer is
	generic(MAX : positive := 300);	--timeout value
	Port ( clk : in std_logic;		--10Hz
		start, reset : in std_logic;		--starts the timer
		timeout : out std_logic); --timer has timed out
end Timer;

architecture Behavioral of Timer is
	signal count : natural range 0 to MAX;
begin
	process(clk, reset) 
	begin	 
		if reset = '1' then
			count <= 0;
		elsif rising_edge(clk) then
			if start = '0' or count = MAX then
				count <= 0;
			else
				count <= count + 1;
			end if;	 
		end if;
	end process;
	timeout <= '1' when count = MAX else '0';
end Behavioral;