txsys.v

比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述

`timescale 1ns / 1ps
//Asynchronous bit-serial transmitter
module txsys #(parameter CLKSPERBIT = 18,
					BITSPERCHAR = 11)
					(	input clock, 
						reset, 
						odd_noteven,
						write,
						input [7:0] datain,
						output reg busy,
						output txdata);

reg q0, q1;
wire write_pulse, bit_time, endchar;

wire [8:0] p_data; //parity &  data

reg [4:0] clkcount;  //bit timer
reg [3:0] bitcount;  //bit counter
reg [10:0] tx_reg;	//shift register

//write pulse synchroniser
always @(posedge clock)
begin
	q0 <= write;
	q1 <= q0;
end

assign write_pulse = q1 & ~q0;
//end of pulse synchroniser

//bit timer
always @(posedge clock)
begin
	if ((write_pulse == 1'b1)||(clkcount == CLKSPERBIT-1))
		clkcount <= 0;	
	else
		clkcount <= clkcount + 1;
end

assign bit_time = (clkcount == CLKSPERBIT-1);
//end of bit timer

//bit counter
always @(posedge clock)
begin
	if ((write_pulse == 1'b1)||(bitcount == BITSPERCHAR))
		bitcount <= 0;
	else if (bit_time)
		bitcount <= bitcount + 1;	
end

assign endchar = (bitcount == BITSPERCHAR);
//end of bit counter

//busy logic
always @(posedge clock)
begin
	if (reset||endchar)
		busy <= 1'b0;
	else if (write_pulse)	
		busy <= 1'b1;
end
//end of busy logic

//parity logic
assign p_data = {(^datain)^odd_noteven, datain};

//shift register
always @(posedge clock)
begin
	if (reset)
		tx_reg <= 11'b11111111111;
	else if (write_pulse)
		tx_reg <= {1'b1, p_data, 1'b0};
	else if (bit_time) begin
		tx_reg <= tx_reg >> 1;
		tx_reg[10] <= 1'b1;
	end
end
//connect serial output
assign txdata = tx_reg[0];
//end shift register

endmodule