par_to_ser.tan.summary

来自「一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.700 ns
From           : rst
To             : lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.200 ns
From           : dp~reg0
To             : dp
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.100 ns
From           : rst
To             : dst[2]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 81.30 MHz ( period = 12.300 ns )
From           : lpm_counter:counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
To             : dp~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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