par_to_ser.map.summary

来自「一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Sat Apr 25 10:17:54 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : par_to_ser
Top-level Entity Name : par_to_ser
Family : FLEX10K
Total logic elements : 20
Total pins : 15
Total memory bits : 0