par_to_ser.fit.summary

一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据

Fitter Status : Successful - Sat Apr 25 10:17:59 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : par_to_ser
Top-level Entity Name : par_to_ser
Family : FLEX10K
Device : EPF10K20TC144-4
Timing Models : Final
Total logic elements : 20 / 1,152 ( 2 % )
Total pins : 15 / 102 ( 15 % )
Total memory bits : 0 / 12,288 ( 0 % )