digital_clk_timesim.vhd

总体演示程序DEMO_FPGA.rar

    port map (
      ADR0 => N24_0,
      ADR1 => c2(7),
      ADR2 => c2(2),
      ADR3 => c2(0),
      O => Ker7_O_pack_1
    );
  Q_n00461 : X_LUT4
    generic map(
      INIT => X"6C2C"
    )
    port map (
      ADR0 => c2(4),
      ADR1 => c2(6),
      ADR2 => c2(5),
      ADR3 => Ker7_O,
      O => Q_n00461_O
    );
  c2_6_XUSED : X_BUF
    port map (
      I => Ker7_O_pack_1,
      O => Ker7_O
    );
  c2_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Q_n00461_O,
      CE => Q_n0087_0,
      CLK => clk_BUFGP,
      SET => c2_6_FFY_SET,
      RST => GND,
      O => c2(6)
    );
  c2_6_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => ireset_IBUF_0,
      O => c2_6_FFY_SET
    );
  Ker6 : X_LUT4
    generic map(
      INIT => X"F7FF"
    )
    port map (
      ADR0 => N22,
      ADR1 => c1(2),
      ADR2 => c1(7),
      ADR3 => c1(1),
      O => Ker6_O_pack_1
    );
  Q_n00551 : X_LUT4
    generic map(
      INIT => X"6A4A"
    )
    port map (
      ADR0 => c1(6),
      ADR1 => c1(4),
      ADR2 => c1(5),
      ADR3 => Ker6_O,
      O => Q_n00551_O
    );
  c1_6_XUSED : X_BUF
    port map (
      I => Ker6_O_pack_1,
      O => Ker6_O
    );
  c1_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n00551_O,
      CE => Q_n0096_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_6_FFY_RST,
      O => c1(6)
    );
  c1_6_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_6_FFY_RST
    );
  Ker17_SW0 : X_LUT4
    generic map(
      INIT => X"FF77"
    )
    port map (
      ADR0 => c1(1),
      ADR1 => c1(2),
      ADR2 => VCC,
      ADR3 => c1(7),
      O => N40_pack_1
    );
  Ker151 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => N108_0,
      ADR1 => c1(6),
      ADR2 => c1(5),
      ADR3 => N40,
      O => N15
    );
  N40_XUSED : X_BUF
    port map (
      I => N40_pack_1,
      O => N40
    );
  N40_YUSED : X_BUF
    port map (
      I => N15,
      O => N15_0
    );
  Ker16 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => N36_0,
      ADR1 => c2(6),
      ADR2 => c2(4),
      ADR3 => c2(5),
      O => N16_pack_1
    );
  Ker181 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => c2(0),
      ADR1 => N15_0,
      ADR2 => c2(3),
      ADR3 => N16,
      O => N18
    );
  N16_XUSED : X_BUF
    port map (
      I => N16_pack_1,
      O => N16
    );
  N16_YUSED : X_BUF
    port map (
      I => N18,
      O => N18_0
    );
  Q_n0087_SW0 : X_LUT4
    generic map(
      INIT => X"100F"
    )
    port map (
      ADR0 => c2(7),
      ADR1 => N126_0,
      ADR2 => c2(1),
      ADR3 => c2(2),
      O => Q_n0087_SW0_O_pack_1
    );
  Q_n0087_13 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => c2(0),
      ADR1 => N15_0,
      ADR2 => c2(3),
      ADR3 => Q_n0087_SW0_O,
      O => Q_n0087
    );
  Q_n0087_SW0_O_XUSED : X_BUF
    port map (
      I => Q_n0087_SW0_O_pack_1,
      O => Q_n0087_SW0_O
    );
  Q_n0087_SW0_O_YUSED : X_BUF
    port map (
      I => Q_n0087,
      O => Q_n0087_0
    );
  c1_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Q_n0050,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => c1_3_FFY_SET,
      RST => GND,
      O => c1(2)
    );
  c1_3_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => ireset_IBUF_0,
      O => c1_3_FFY_SET
    );
  c1_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0054,
      CE => Q_n0096_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_7_FFY_RST,
      O => c1(5)
    );
  c1_7_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_7_FFY_RST
    );
  c2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0041,
      CE => N15_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_3_FFY_RST,
      O => c2(2)
    );
  c2_3_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_3_FFY_RST
    );
  c3_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0036,
      CE => Q_n0078_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_7_FFY_RST,
      O => c3(6)
    );
  c3_7_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_7_FFY_RST
    );
  ireset_IMUX : X_BUF
    port map (
      I => ireset_IBUF,
      O => ireset_IBUF_0
    );
  ireset_IBUF_14 : X_BUF
    port map (
      I => ireset,
      O => ireset_IBUF
    );
  om_0_OBUF : X_TRI
    port map (
      I => om_0_OUTMUX,
      CTL => om_0_ENABLE,
      O => om(0)
    );
  om_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_0_ENABLE
    );
  om_0_OUTMUX_15 : X_BUF
    port map (
      I => c2(0),
      O => om_0_OUTMUX
    );
  om_1_OBUF : X_TRI
    port map (
      I => om_1_OUTMUX,
      CTL => om_1_ENABLE,
      O => om(1)
    );
  om_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_1_ENABLE
    );
  om_1_OUTMUX_16 : X_BUF
    port map (
      I => c2(1),
      O => om_1_OUTMUX
    );
  om_2_OBUF : X_TRI
    port map (
      I => om_2_OUTMUX,
      CTL => om_2_ENABLE,
      O => om(2)
    );
  om_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_2_ENABLE
    );
  om_2_OUTMUX_17 : X_BUF
    port map (
      I => c2(2),
      O => om_2_OUTMUX
    );
  om_3_OBUF : X_TRI
    port map (
      I => om_3_OUTMUX,
      CTL => om_3_ENABLE,
      O => om(3)
    );
  om_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_3_ENABLE
    );
  om_3_OUTMUX_18 : X_BUF
    port map (
      I => c2(3),
      O => om_3_OUTMUX
    );
  om_4_OBUF : X_TRI
    port map (
      I => om_4_OUTMUX,
      CTL => om_4_ENABLE,
      O => om(4)
    );
  om_4_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_4_ENABLE
    );
  om_4_OUTMUX_19 : X_BUF
    port map (
      I => c2(4),
      O => om_4_OUTMUX
    );
  om_5_OBUF : X_TRI
    port map (
      I => om_5_OUTMUX,
      CTL => om_5_ENABLE,
      O => om(5)
    );
  om_5_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_5_ENABLE
    );
  om_5_OUTMUX_20 : X_BUF
    port map (
      I => c2(5),
      O => om_5_OUTMUX
    );
  om_6_OBUF : X_TRI
    port map (
      I => om_6_OUTMUX,
      CTL => om_6_ENABLE,
      O => om(6)
    );
  om_6_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_6_ENABLE
    );
  om_6_OUTMUX_21 : X_BUF
    port map (
      I => c2(6),
      O => om_6_OUTMUX
    );
  om_7_OBUF : X_TRI
    port map (
      I => om_7_OUTMUX,
      CTL => om_7_ENABLE,
      O => om(7)
    );
  om_7_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => om_7_ENABLE
    );
  om_7_OUTMUX_22 : X_BUF
    port map (
      I => c2(7),
      O => om_7_OUTMUX
    );
  os_0_OBUF : X_TRI
    port map (
      I => os_0_OUTMUX,
      CTL => os_0_ENABLE,
      O => os(0)
    );
  os_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_0_ENABLE
    );
  os_0_OUTMUX_23 : X_BUF
    port map (
      I => c1(0),
      O => os_0_OUTMUX
    );
  os_1_OBUF : X_TRI
    port map (
      I => os_1_OUTMUX,
      CTL => os_1_ENABLE,
      O => os(1)
    );
  os_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_1_ENABLE
    );
  os_1_OUTMUX_24 : X_BUF
    port map (
      I => c1(1),
      O => os_1_OUTMUX
    );
  os_2_OBUF : X_TRI
    port map (
      I => os_2_OUTMUX,
      CTL => os_2_ENABLE,
      O => os(2)
    );
  os_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_2_ENABLE
    );
  os_2_OUTMUX_25 : X_BUF
    port map (
      I => c1(2),
      O => os_2_OUTMUX
    );
  os_3_OBUF : X_TRI
    port map (
      I => os_3_OUTMUX,
      CTL => os_3_ENABLE,
      O => os(3)
    );
  os_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_3_ENABLE
    );
  os_3_OUTMUX_26 : X_BUF
    port map (
      I => c1(3),
      O => os_3_OUTMUX
    );
  os_4_OBUF : X_TRI
    port map (
      I => os_4_OUTMUX,
      CTL => os_4_ENABLE,
      O => os(4)
    );
  os_4_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_4_ENABLE
    );
  os_4_OUTMUX_27 : X_BUF
    port map (
      I => c1(4),
      O => os_4_OUTMUX
    );
  c1_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0051,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_3_FFX_RST,
      O => c1(3)
    );
  c1_3_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_3_FFX_RST
    );
  c1_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0056,
      CE => Q_n0096_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_7_FFX_RST,
      O => c1(7)
    );
  c1_7_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_7_FFX_RST
    );
  c2_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0042,
      CE => N15_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_3_FFX_RST,
      O => c2(3)
    );
  c2_3_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_3_FFX_RST
    );
  c1_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => c1_0_BXMUXNOT,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => c1_0_FFX_SET,
      RST => GND,
      O => c1(0)
    );
  c1_0_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => ireset_IBUF_0,
      O => c1_0_FFX_SET
    );
  c2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c2_0_BXMUXNOT,
      CE => N15_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_0_FFX_RST,
      O => c2(0)
    );
  c2_0_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_0_FFX_RST
    );
  c3_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => c3_0_BXMUXNOT,
      CE => N18_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_0_FFX_RST,
      O => c3(0)
    );
  c3_0_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_0_FFX_RST
    );
  clk_BUFGP_BUFG_BUF : X_CKBUF
    port map (
      I => clk,
      O => clk_BUFGP
    );
  NlwBlock_digital_clk_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_digital_clk_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;