digital_clk_timesim.vhd

来自「总体演示程序DEMO_FPGA.rar」· VHDL 代码 · 共 1,810 行 · 第 1/3 页

      I => c3(0),
      O => c3_0_BXMUXNOT
    );
  c3_0_XUSED : X_BUF
    port map (
      I => CHOICE292,
      O => CHOICE292_0
    );
  c3_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0058,
      CE => N18_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_0_FFY_RST,
      O => c3(1)
    );
  c3_0_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_0_FFY_RST
    );
  Ker4_SW0 : X_LUT4
    generic map(
      INIT => X"FDFD"
    )
    port map (
      ADR0 => c3(0),
      ADR1 => c3(2),
      ADR2 => c3(6),
      ADR3 => VCC,
      O => N26
    );
  N26_YUSED : X_BUF
    port map (
      I => N26,
      O => N26_0
    );
  Ker4_SW1 : X_LUT4
    generic map(
      INIT => X"0404"
    )
    port map (
      ADR0 => c3(3),
      ADR1 => c3(1),
      ADR2 => c3(7),
      ADR3 => VCC,
      O => N114_pack_1
    );
  Q_n00351 : X_LUT4
    generic map(
      INIT => X"6466"
    )
    port map (
      ADR0 => c3(5),
      ADR1 => c3(4),
      ADR2 => N26_0,
      ADR3 => N114,
      O => Q_n0035
    );
  c3_5_XUSED : X_BUF
    port map (
      I => N114_pack_1,
      O => N114
    );
  c3_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0035,
      CE => Q_n0078_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_5_FFY_RST,
      O => c3(5)
    );
  c3_5_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_5_FFY_RST
    );
  Ker7_SW0 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => c2(3),
      ADR1 => c2(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N24
    );
  Ker16_SW0 : X_LUT4
    generic map(
      INIT => X"FF77"
    )
    port map (
      ADR0 => c2(2),
      ADR1 => c2(1),
      ADR2 => VCC,
      ADR3 => c2(7),
      O => N36
    );
  N24_XUSED : X_BUF
    port map (
      I => N24,
      O => N24_0
    );
  N24_YUSED : X_BUF
    port map (
      I => N36,
      O => N36_0
    );
  Ker4_SW2 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c3(5),
      ADR2 => c3(3),
      ADR3 => c3(1),
      O => N116_pack_1
    );
  Q_n00341 : X_LUT4
    generic map(
      INIT => X"0E0F"
    )
    port map (
      ADR0 => c3(7),
      ADR1 => N26_0,
      ADR2 => c3(4),
      ADR3 => N116,
      O => Q_n0034
    );
  c3_4_XUSED : X_BUF
    port map (
      I => N116_pack_1,
      O => N116
    );
  c3_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0034,
      CE => Q_n0078_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_4_FFY_RST,
      O => c3(4)
    );
  c3_4_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_4_FFY_RST
    );
  Ker17_SW1 : X_LUT4
    generic map(
      INIT => X"DDFF"
    )
    port map (
      ADR0 => c1(3),
      ADR1 => c1(4),
      ADR2 => VCC,
      ADR3 => c1(0),
      O => N108
    );
  N108_YUSED : X_BUF
    port map (
      I => N108,
      O => N108_0
    );
  Ker6_SW2 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => c1(5),
      ADR1 => c1(6),
      ADR2 => c1(1),
      ADR3 => c1(2),
      O => N120
    );
  Ker6_SW1 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )
    port map (
      ADR0 => c1(6),
      ADR1 => c1(7),
      ADR2 => c1(1),
      ADR3 => c1(2),
      O => N118
    );
  N120_XUSED : X_BUF
    port map (
      I => N120,
      O => N120_0
    );
  N120_YUSED : X_BUF
    port map (
      I => N118,
      O => N118_0
    );
  Q_n003135_SW1 : X_LUT4
    generic map(
      INIT => X"B555"
    )
    port map (
      ADR0 => c3(2),
      ADR1 => c3(3),
      ADR2 => c3(0),
      ADR3 => c3(1),
      O => N129_pack_1
    );
  Q_n003135 : X_LUT4
    generic map(
      INIT => X"515D"
    )
    port map (
      ADR0 => N128_0,
      ADR1 => c3(5),
      ADR2 => CHOICE284_0,
      ADR3 => N129,
      O => Q_n0031
    );
  c3_2_XUSED : X_BUF
    port map (
      I => N129_pack_1,
      O => N129
    );
  c3_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0031,
      CE => N18_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_2_FFY_RST,
      O => c3(2)
    );
  c3_2_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_2_FFY_RST
    );
  os_5_OBUF : X_TRI
    port map (
      I => os_5_OUTMUX,
      CTL => os_5_ENABLE,
      O => os(5)
    );
  os_5_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_5_ENABLE
    );
  os_5_OUTMUX_2 : X_BUF
    port map (
      I => c1(5),
      O => os_5_OUTMUX
    );
  os_6_OBUF : X_TRI
    port map (
      I => os_6_OUTMUX,
      CTL => os_6_ENABLE,
      O => os(6)
    );
  os_6_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_6_ENABLE
    );
  os_6_OUTMUX_3 : X_BUF
    port map (
      I => c1(6),
      O => os_6_OUTMUX
    );
  oh_0_OBUF : X_TRI
    port map (
      I => oh_0_OUTMUX,
      CTL => oh_0_ENABLE,
      O => oh(0)
    );
  oh_0_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_0_ENABLE
    );
  oh_0_OUTMUX_4 : X_BUF
    port map (
      I => c3(0),
      O => oh_0_OUTMUX
    );
  os_7_OBUF : X_TRI
    port map (
      I => os_7_OUTMUX,
      CTL => os_7_ENABLE,
      O => os(7)
    );
  os_7_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => os_7_ENABLE
    );
  os_7_OUTMUX_5 : X_BUF
    port map (
      I => c1(7),
      O => os_7_OUTMUX
    );
  oh_1_OBUF : X_TRI
    port map (
      I => oh_1_OUTMUX,
      CTL => oh_1_ENABLE,
      O => oh(1)
    );
  oh_1_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_1_ENABLE
    );
  oh_1_OUTMUX_6 : X_BUF
    port map (
      I => c3(1),
      O => oh_1_OUTMUX
    );
  oh_2_OBUF : X_TRI
    port map (
      I => oh_2_OUTMUX,
      CTL => oh_2_ENABLE,
      O => oh(2)
    );
  oh_2_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_2_ENABLE
    );
  oh_2_OUTMUX_7 : X_BUF
    port map (
      I => c3(2),
      O => oh_2_OUTMUX
    );
  oh_3_OBUF : X_TRI
    port map (
      I => oh_3_OUTMUX,
      CTL => oh_3_ENABLE,
      O => oh(3)
    );
  oh_3_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_3_ENABLE
    );
  oh_3_OUTMUX_8 : X_BUF
    port map (
      I => c3(3),
      O => oh_3_OUTMUX
    );
  oh_4_OBUF : X_TRI
    port map (
      I => oh_4_OUTMUX,
      CTL => oh_4_ENABLE,
      O => oh(4)
    );
  oh_4_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_4_ENABLE
    );
  oh_4_OUTMUX_9 : X_BUF
    port map (
      I => c3(4),
      O => oh_4_OUTMUX
    );
  oh_5_OBUF : X_TRI
    port map (
      I => oh_5_OUTMUX,
      CTL => oh_5_ENABLE,
      O => oh(5)
    );
  oh_5_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_5_ENABLE
    );
  oh_5_OUTMUX_10 : X_BUF
    port map (
      I => c3(5),
      O => oh_5_OUTMUX
    );
  oh_6_OBUF : X_TRI
    port map (
      I => oh_6_OUTMUX,
      CTL => oh_6_ENABLE,
      O => oh(6)
    );
  oh_6_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_6_ENABLE
    );
  oh_6_OUTMUX_11 : X_BUF
    port map (
      I => c3(6),
      O => oh_6_OUTMUX
    );
  oh_7_OBUF : X_TRI
    port map (
      I => oh_7_OUTMUX,
      CTL => oh_7_ENABLE,
      O => oh(7)
    );
  oh_7_ENABLEINV : X_INV
    port map (
      I => GTS,
      O => oh_7_ENABLE
    );
  oh_7_OUTMUX_12 : X_BUF
    port map (
      I => c3(7),
      O => oh_7_OUTMUX
    );
  Ker7_SW2 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => c2(2),
      ADR1 => c2(5),
      ADR2 => c2(6),
      ADR3 => c2(0),
      O => Ker7_SW2_O_pack_1
    );
  Q_n00441 : X_LUT4
    generic map(
      INIT => X"0D0F"
    )
    port map (
      ADR0 => N24_0,
      ADR1 => c2(7),
      ADR2 => c2(4),
      ADR3 => Ker7_SW2_O,
      O => Q_n0044
    );
  c2_4_XUSED : X_BUF
    port map (
      I => Ker7_SW2_O_pack_1,
      O => Ker7_SW2_O
    );
  c2_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0044,
      CE => Q_n0087_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_4_FFY_RST,
      O => c2(4)
    );
  c2_4_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_4_FFY_RST
    );
  Q_n007842 : X_LUT4
    generic map(
      INIT => X"0A20"
    )
    port map (
      ADR0 => CHOICE292_0,
      ADR1 => N112_0,
      ADR2 => c3(1),
      ADR3 => c3(3),
      O => Q_n007842_O_pack_1
    );
  Q_n007854 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => N15_0,
      ADR1 => N106_0,
      ADR2 => N16,
      ADR3 => Q_n007842_O,
      O => Q_n0078
    );
  Q_n007842_O_XUSED : X_BUF
    port map (
      I => Q_n007842_O_pack_1,
      O => Q_n007842_O
    );
  Q_n007842_O_YUSED : X_BUF
    port map (
      I => Q_n0078,
      O => Q_n0078_0
    );
  Ker7_SW1 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => c2(2),
      ADR1 => c2(0),
      ADR2 => c2(7),
      ADR3 => c2(6),
      O => Ker7_SW1_O_pack_1
    );
  Q_n00451 : X_LUT4
    generic map(
      INIT => X"1A5A"
    )
    port map (
      ADR0 => c2(4),
      ADR1 => N24_0,
      ADR2 => c2(5),
      ADR3 => Ker7_SW1_O,
      O => Q_n0045
    );
  c2_5_XUSED : X_BUF
    port map (
      I => Ker7_SW1_O_pack_1,
      O => Ker7_SW1_O
    );
  c2_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0045,
      CE => Q_n0087_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_5_FFY_RST,
      O => c2(5)
    );
  c2_5_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_5_FFY_RST
    );
  Ker6_SW0 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c1(0),
      ADR2 => VCC,
      ADR3 => c1(3),
      O => N22_pack_1
    );
  Q_n00531 : X_LUT4
    generic map(
      INIT => X"3133"
    )
    port map (
      ADR0 => N120_0,
      ADR1 => c1(4),
      ADR2 => c1(7),
      ADR3 => N22,
      O => Q_n0053
    );
  c1_4_XUSED : X_BUF
    port map (
      I => N22_pack_1,
      O => N22
    );
  c1_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0053,
      CE => Q_n0096_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_4_FFY_RST,
      O => c1(4)
    );
  c1_4_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_4_FFY_RST
    );
  Ker7 : X_LUT4
    generic map(
      INIT => X"DFFF"
    )