digital_clk_timesim.vhd

总体演示程序DEMO_FPGA.rar

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.39
--  \   \         Application: netgen
--  /   /         Filename: digital_clk_timesim.vhd
-- /___/   /\     Timestamp: Fri Mar 25 03:08:11 2005
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 6 -pcf digital_clk.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim digital_clk.ncd digital_clk_timesim.vhd 
-- Device	: 2s100epq208-6 (PRODUCTION 1.18 2005-01-22)
-- Input file	: digital_clk.ncd
-- Output file	: digital_clk_timesim.vhd
-- # of Entities	: 1
-- Design Name	: digital_clk
-- Xilinx	: E:/Program/EDA/Xilinx
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity digital_clk is
  port (
    clk : in STD_LOGIC := 'X'; 
    ireset : in STD_LOGIC := 'X'; 
    oh : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    om : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    os : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end digital_clk;

architecture Structure of digital_clk is
  signal clk_BUFGP : STD_LOGIC; 
  signal Q_n0087_0 : STD_LOGIC; 
  signal N24_0 : STD_LOGIC; 
  signal Ker7_SW2_O : STD_LOGIC; 
  signal ireset_IBUF_0 : STD_LOGIC; 
  signal CHOICE292_0 : STD_LOGIC; 
  signal N112_0 : STD_LOGIC; 
  signal N15_0 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal Q_n007842_O : STD_LOGIC; 
  signal N106_0 : STD_LOGIC; 
  signal Q_n0078_0 : STD_LOGIC; 
  signal Ker7_SW1_O : STD_LOGIC; 
  signal Q_n0096_0 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N120_0 : STD_LOGIC; 
  signal Ker7_O : STD_LOGIC; 
  signal Ker6_O : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal N108_0 : STD_LOGIC; 
  signal N36_0 : STD_LOGIC; 
  signal N18_0 : STD_LOGIC; 
  signal N126_0 : STD_LOGIC; 
  signal Q_n0087_SW0_O : STD_LOGIC; 
  signal N20_0 : STD_LOGIC; 
  signal Ker17_O : STD_LOGIC; 
  signal N118_0 : STD_LOGIC; 
  signal N128_0 : STD_LOGIC; 
  signal CHOICE284_0 : STD_LOGIC; 
  signal N26_0 : STD_LOGIC; 
  signal N114 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal N129 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Ker17_O_pack_1 : STD_LOGIC; 
  signal Q_n0096 : STD_LOGIC; 
  signal Q_n0051 : STD_LOGIC; 
  signal Q_n0050 : STD_LOGIC; 
  signal Q_n0056 : STD_LOGIC; 
  signal Q_n0054 : STD_LOGIC; 
  signal Q_n0042 : STD_LOGIC; 
  signal Q_n0041 : STD_LOGIC; 
  signal N128 : STD_LOGIC; 
  signal Q_n0032 : STD_LOGIC; 
  signal c3_3_FFY_SET : STD_LOGIC; 
  signal N126 : STD_LOGIC; 
  signal Q_n0047 : STD_LOGIC; 
  signal c2_7_FFY_RST : STD_LOGIC; 
  signal Q_n0037 : STD_LOGIC; 
  signal Q_n0036 : STD_LOGIC; 
  signal c3_7_FFX_RST : STD_LOGIC; 
  signal c1_0_BXMUXNOT : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal Q_n0049 : STD_LOGIC; 
  signal c1_0_FFY_RST : STD_LOGIC; 
  signal CHOICE284 : STD_LOGIC; 
  signal N112 : STD_LOGIC; 
  signal c2_0_BXMUXNOT : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal Q_n0040 : STD_LOGIC; 
  signal c2_0_FFY_RST : STD_LOGIC; 
  signal c3_0_BXMUXNOT : STD_LOGIC; 
  signal CHOICE292 : STD_LOGIC; 
  signal Q_n0058 : STD_LOGIC; 
  signal c3_0_FFY_RST : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N114_pack_1 : STD_LOGIC; 
  signal Q_n0035 : STD_LOGIC; 
  signal c3_5_FFY_RST : STD_LOGIC; 
  signal N24 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal N116_pack_1 : STD_LOGIC; 
  signal Q_n0034 : STD_LOGIC; 
  signal c3_4_FFY_RST : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N118 : STD_LOGIC; 
  signal N129_pack_1 : STD_LOGIC; 
  signal Q_n0031 : STD_LOGIC; 
  signal c3_2_FFY_RST : STD_LOGIC; 
  signal os_5_ENABLE : STD_LOGIC; 
  signal os_5_OUTMUX : STD_LOGIC; 
  signal os_6_ENABLE : STD_LOGIC; 
  signal os_6_OUTMUX : STD_LOGIC; 
  signal oh_0_ENABLE : STD_LOGIC; 
  signal oh_0_OUTMUX : STD_LOGIC; 
  signal os_7_ENABLE : STD_LOGIC; 
  signal os_7_OUTMUX : STD_LOGIC; 
  signal oh_1_ENABLE : STD_LOGIC; 
  signal oh_1_OUTMUX : STD_LOGIC; 
  signal oh_2_ENABLE : STD_LOGIC; 
  signal oh_2_OUTMUX : STD_LOGIC; 
  signal oh_3_ENABLE : STD_LOGIC; 
  signal oh_3_OUTMUX : STD_LOGIC; 
  signal oh_4_ENABLE : STD_LOGIC; 
  signal oh_4_OUTMUX : STD_LOGIC; 
  signal oh_5_ENABLE : STD_LOGIC; 
  signal oh_5_OUTMUX : STD_LOGIC; 
  signal oh_6_ENABLE : STD_LOGIC; 
  signal oh_6_OUTMUX : STD_LOGIC; 
  signal oh_7_ENABLE : STD_LOGIC; 
  signal oh_7_OUTMUX : STD_LOGIC; 
  signal Ker7_SW2_O_pack_1 : STD_LOGIC; 
  signal Q_n0044 : STD_LOGIC; 
  signal c2_4_FFY_RST : STD_LOGIC; 
  signal Q_n007842_O_pack_1 : STD_LOGIC; 
  signal Q_n0078 : STD_LOGIC; 
  signal Ker7_SW1_O_pack_1 : STD_LOGIC; 
  signal Q_n0045 : STD_LOGIC; 
  signal c2_5_FFY_RST : STD_LOGIC; 
  signal N22_pack_1 : STD_LOGIC; 
  signal Q_n0053 : STD_LOGIC; 
  signal c1_4_FFY_RST : STD_LOGIC; 
  signal Ker7_O_pack_1 : STD_LOGIC; 
  signal Q_n00461_O : STD_LOGIC; 
  signal c2_6_FFY_SET : STD_LOGIC; 
  signal Ker6_O_pack_1 : STD_LOGIC; 
  signal Q_n00551_O : STD_LOGIC; 
  signal c1_6_FFY_RST : STD_LOGIC; 
  signal N40_pack_1 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal N16_pack_1 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal Q_n0087_SW0_O_pack_1 : STD_LOGIC; 
  signal Q_n0087 : STD_LOGIC; 
  signal c1_3_FFY_SET : STD_LOGIC; 
  signal c1_7_FFY_RST : STD_LOGIC; 
  signal c2_3_FFY_RST : STD_LOGIC; 
  signal c3_7_FFY_RST : STD_LOGIC; 
  signal ireset_IBUF : STD_LOGIC; 
  signal om_0_ENABLE : STD_LOGIC; 
  signal om_0_OUTMUX : STD_LOGIC; 
  signal om_1_ENABLE : STD_LOGIC; 
  signal om_1_OUTMUX : STD_LOGIC; 
  signal om_2_ENABLE : STD_LOGIC; 
  signal om_2_OUTMUX : STD_LOGIC; 
  signal om_3_ENABLE : STD_LOGIC; 
  signal om_3_OUTMUX : STD_LOGIC; 
  signal om_4_ENABLE : STD_LOGIC; 
  signal om_4_OUTMUX : STD_LOGIC; 
  signal om_5_ENABLE : STD_LOGIC; 
  signal om_5_OUTMUX : STD_LOGIC; 
  signal om_6_ENABLE : STD_LOGIC; 
  signal om_6_OUTMUX : STD_LOGIC; 
  signal om_7_ENABLE : STD_LOGIC; 
  signal om_7_OUTMUX : STD_LOGIC; 
  signal os_0_ENABLE : STD_LOGIC; 
  signal os_0_OUTMUX : STD_LOGIC; 
  signal os_1_ENABLE : STD_LOGIC; 
  signal os_1_OUTMUX : STD_LOGIC; 
  signal os_2_ENABLE : STD_LOGIC; 
  signal os_2_OUTMUX : STD_LOGIC; 
  signal os_3_ENABLE : STD_LOGIC; 
  signal os_3_OUTMUX : STD_LOGIC; 
  signal os_4_ENABLE : STD_LOGIC; 
  signal os_4_OUTMUX : STD_LOGIC; 
  signal c1_3_FFX_RST : STD_LOGIC; 
  signal c1_7_FFX_RST : STD_LOGIC; 
  signal c2_3_FFX_RST : STD_LOGIC; 
  signal c1_0_FFX_SET : STD_LOGIC; 
  signal c2_0_FFX_RST : STD_LOGIC; 
  signal c3_0_FFX_RST : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal c1 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal c3 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal c2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  Ker17 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => c1(6),
      ADR1 => c1(4),
      ADR2 => N40,
      ADR3 => c1(5),
      O => Ker17_O_pack_1
    );
  Q_n0096_1 : X_LUT4
    generic map(
      INIT => X"5501"
    )
    port map (
      ADR0 => N20_0,
      ADR1 => c1(2),
      ADR2 => c1(1),
      ADR3 => Ker17_O,
      O => Q_n0096
    );
  Ker17_O_XUSED : X_BUF
    port map (
      I => Ker17_O_pack_1,
      O => Ker17_O
    );
  Ker17_O_YUSED : X_BUF
    port map (
      I => Q_n0096,
      O => Q_n0096_0
    );
  Q_n00511 : X_LUT4
    generic map(
      INIT => X"68CC"
    )
    port map (
      ADR0 => c1(2),
      ADR1 => c1(3),
      ADR2 => c1(1),
      ADR3 => c1(0),
      O => Q_n0051
    );
  Q_n00501 : X_LUT4
    generic map(
      INIT => X"7788"
    )
    port map (
      ADR0 => c1(1),
      ADR1 => c1(0),
      ADR2 => VCC,
      ADR3 => c1(2),
      O => Q_n0050
    );
  Q_n00561 : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => c1(6),
      ADR1 => c1(7),
      ADR2 => c1(5),
      ADR3 => c1(4),
      O => Q_n0056
    );
  Q_n00541 : X_LUT4
    generic map(
      INIT => X"558A"
    )
    port map (
      ADR0 => c1(5),
      ADR1 => N118_0,
      ADR2 => N22,
      ADR3 => c1(4),
      O => Q_n0054
    );
  Q_n00421 : X_LUT4
    generic map(
      INIT => X"6AA2"
    )
    port map (
      ADR0 => c2(3),
      ADR1 => c2(0),
      ADR2 => c2(2),
      ADR3 => c2(1),
      O => Q_n0042
    );
  Q_n00411 : X_LUT4
    generic map(
      INIT => X"3FC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c2(1),
      ADR2 => c2(0),
      ADR3 => c2(2),
      O => Q_n0041
    );
  Q_n003135_SW0 : X_LUT4
    generic map(
      INIT => X"9933"
    )
    port map (
      ADR0 => c3(1),
      ADR1 => c3(2),
      ADR2 => VCC,
      ADR3 => c3(0),
      O => N128
    );
  Q_n00321 : X_LUT4
    generic map(
      INIT => X"78D0"
    )
    port map (
      ADR0 => c3(0),
      ADR1 => c3(1),
      ADR2 => c3(3),
      ADR3 => c3(2),
      O => Q_n0032
    );
  c3_3_XUSED : X_BUF
    port map (
      I => N128,
      O => N128_0
    );
  c3_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Q_n0032,
      CE => N18_0,
      CLK => clk_BUFGP,
      SET => c3_3_FFY_SET,
      RST => GND,
      O => c3(3)
    );
  c3_3_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => ireset_IBUF_0,
      O => c3_3_FFY_SET
    );
  Q_n0087_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c2(6),
      ADR2 => c2(5),
      ADR3 => c2(4),
      O => N126
    );
  Q_n00471 : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => c2(6),
      ADR1 => c2(7),
      ADR2 => c2(5),
      ADR3 => c2(4),
      O => Q_n0047
    );
  c2_7_XUSED : X_BUF
    port map (
      I => N126,
      O => N126_0
    );
  c2_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0047,
      CE => Q_n0087_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_7_FFY_RST,
      O => c2(7)
    );
  c2_7_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_7_FFY_RST
    );
  Q_n00371 : X_LUT4
    generic map(
      INIT => X"6CCC"
    )
    port map (
      ADR0 => c3(5),
      ADR1 => c3(7),
      ADR2 => c3(6),
      ADR3 => c3(4),
      O => Q_n0037
    );
  Q_n00361 : X_LUT4
    generic map(
      INIT => X"3FC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c3(5),
      ADR2 => c3(4),
      ADR3 => c3(6),
      O => Q_n0036
    );
  c3_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0037,
      CE => Q_n0078_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c3_7_FFX_RST,
      O => c3(7)
    );
  c3_7_FFX_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c3_7_FFX_RST
    );
  Q_n0096_SW0 : X_LUT4
    generic map(
      INIT => X"5F5F"
    )
    port map (
      ADR0 => c1(3),
      ADR1 => VCC,
      ADR2 => c1(0),
      ADR3 => VCC,
      O => N20
    );
  Q_n00491 : X_LUT4
    generic map(
      INIT => X"3C34"
    )
    port map (
      ADR0 => c1(3),
      ADR1 => c1(0),
      ADR2 => c1(1),
      ADR3 => c1(2),
      O => Q_n0049
    );
  c1_0_BXMUX : X_INV
    port map (
      I => c1(0),
      O => c1_0_BXMUXNOT
    );
  c1_0_XUSED : X_BUF
    port map (
      I => N20,
      O => N20_0
    );
  c1_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0049,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c1_0_FFY_RST,
      O => c1(1)
    );
  c1_0_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c1_0_FFY_RST
    );
  Q_n003112 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c3(4),
      ADR2 => c3(7),
      ADR3 => c3(6),
      O => CHOICE284
    );
  Q_n007842_SW0 : X_LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      ADR0 => c3(6),
      ADR1 => c3(4),
      ADR2 => c3(5),
      ADR3 => c3(7),
      O => N112
    );
  CHOICE284_XUSED : X_BUF
    port map (
      I => CHOICE284,
      O => CHOICE284_0
    );
  CHOICE284_YUSED : X_BUF
    port map (
      I => N112,
      O => N112_0
    );
  Ker181_SW0 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => c2(3),
      ADR1 => c2(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N106
    );
  Q_n00401 : X_LUT4
    generic map(
      INIT => X"3C1C"
    )
    port map (
      ADR0 => c2(3),
      ADR1 => c2(1),
      ADR2 => c2(0),
      ADR3 => c2(2),
      O => Q_n0040
    );
  c2_0_BXMUX : X_INV
    port map (
      I => c2(0),
      O => c2_0_BXMUXNOT
    );
  c2_0_XUSED : X_BUF
    port map (
      I => N106,
      O => N106_0
    );
  c2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0040,
      CE => N15_0,
      CLK => clk_BUFGP,
      SET => GND,
      RST => c2_0_FFY_RST,
      O => c2(1)
    );
  c2_0_FFY_RSTOR : X_OR2
    port map (
      I0 => ireset_IBUF_0,
      I1 => GSR,
      O => c2_0_FFY_RST
    );
  Q_n00782 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => c3(0),
      ADR2 => VCC,
      ADR3 => c3(2),
      O => CHOICE292
    );
  Q_n00581 : X_LUT4
    generic map(
      INIT => X"338C"
    )
    port map (
      ADR0 => c3(2),
      ADR1 => c3(0),
      ADR2 => c3(3),
      ADR3 => c3(1),
      O => Q_n0058
    );
  c3_0_BXMUX : X_INV
    port map (