clk.sim.rpt

一个时钟计数器

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+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      36.55 % ;
; Total nodes checked                                 ; 324          ;
; Total output ports checked                          ; 342          ;
; Total output ports with complete 1/0-value coverage ; 125          ;
; Total output ports with no 1/0-value coverage       ; 203          ;
; Total output ports with no 1-value coverage         ; 208          ;
; Total output ports with no 0-value coverage         ; 212          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                         ;
+------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; Node Name                                                                    ; Output Port Name                                                                  ; Output Port Type ;
+------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; |clk|clkin                                                                   ; |clk|clkin                                                                        ; out              ;
; |clk|seg1[0]                                                                 ; |clk|seg1[0]                                                                      ; pin_out          ;
; |clk|seg1[1]                                                                 ; |clk|seg1[1]                                                                      ; pin_out          ;
; |clk|seg1[2]                                                                 ; |clk|seg1[2]                                                                      ; pin_out          ;
; |clk|seg1[3]                                                                 ; |clk|seg1[3]                                                                      ; pin_out          ;
; |clk|seg2[0]                                                                 ; |clk|seg2[0]                                                                      ; pin_out          ;
; |clk|seg2[1]                                                                 ; |clk|seg2[1]                                                                      ; pin_out          ;
; |clk|seg2[2]                                                                 ; |clk|seg2[2]                                                                      ; pin_out          ;
; |clk|seg3[0]                                                                 ; |clk|seg3[0]                                                                      ; pin_out          ;
; |clk|seg3[1]                                                                 ; |clk|seg3[1]                                                                      ; pin_out          ;
; |clk|seg3[2]                                                                 ; |clk|seg3[2]                                                                      ; pin_out          ;
; |clk|seg3[3]                                                                 ; |clk|seg3[3]                                                                      ; pin_out          ;
; |clk|fen60:u3|tem1~0                                                         ; |clk|fen60:u3|tem1~0                                                              ; out              ;
; |clk|fen60:u3|tem1~1                                                         ; |clk|fen60:u3|tem1~1                                                              ; out              ;
; |clk|fen60:u3|tem1~2                                                         ; |clk|fen60:u3|tem1~2                                                              ; out              ;
; |clk|fen60:u3|tem1~3                                                         ; |clk|fen60:u3|tem1~3                                                              ; out              ;
; |clk|fen60:u3|tem1[0]                                                        ; |clk|fen60:u3|tem1[0]                                                             ; out              ;
; |clk|fen60:u3|tem1[1]                                                        ; |clk|fen60:u3|tem1[1]                                                             ; out              ;
; |clk|fen60:u3|tem1[2]                                                        ; |clk|fen60:u3|tem1[2]                                                             ; out              ;
; |clk|fen60:u3|tem1[3]                                                        ; |clk|fen60:u3|tem1[3]                                                             ; out              ;
; |clk|fen60:u2|carry                                                          ; |clk|fen60:u2|carry                                                               ; out              ;
; |clk|fen60:u2|tem2~0                                                         ; |clk|fen60:u2|tem2~0                                                              ; out              ;
; |clk|fen60:u2|tem2~1                                                         ; |clk|fen60:u2|tem2~1                                                              ; out              ;
; |clk|fen60:u2|tem2~2                                                         ; |clk|fen60:u2|tem2~2                                                              ; out              ;
; |clk|fen60:u2|tem2~3                                                         ; |clk|fen60:u2|tem2~3                                                              ; out              ;
; |clk|fen60:u2|tem1~0                                                         ; |clk|fen60:u2|tem1~0                                                              ; out              ;
; |clk|fen60:u2|tem1~1                                                         ; |clk|fen60:u2|tem1~1                                                              ; out              ;
; |clk|fen60:u2|tem1~2                                                         ; |clk|fen60:u2|tem1~2                                                              ; out              ;
; |clk|fen60:u2|tem1~3                                                         ; |clk|fen60:u2|tem1~3                                                              ; out              ;
; |clk|fen60:u2|tem2[0]                                                        ; |clk|fen60:u2|tem2[0]                                                             ; out              ;
; |clk|fen60:u2|tem2[1]                                                        ; |clk|fen60:u2|tem2[1]                                                             ; out              ;
; |clk|fen60:u2|tem2[2]                                                        ; |clk|fen60:u2|tem2[2]                                                             ; out              ;
; |clk|fen60:u2|tem1[0]                                                        ; |clk|fen60:u2|tem1[0]                                                             ; out              ;
; |clk|fen60:u2|tem1[1]                                                        ; |clk|fen60:u2|tem1[1]                                                             ; out              ;
; |clk|fen60:u2|tem1[2]                                                        ; |clk|fen60:u2|tem1[2]                                                             ; out              ;
; |clk|fen60:u2|tem1[3]                                                        ; |clk|fen60:u2|tem1[3]                                                             ; out              ;
; |clk|fen60:u3|Equal0~5                                                       ; |clk|fen60:u3|Equal0~5                                                            ; out0             ;
; |clk|fen60:u2|Equal0~5                                                       ; |clk|fen60:u2|Equal0~5                                                            ; out0             ;
; |clk|fen60:u2|Equal1~5                                                       ; |clk|fen60:u2|Equal1~5                                                            ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|result_node[0]                                ; |clk|fen60:u2|lpm_add_sub:Add1|result_node[0]                                     ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|result_node[1]                                ; |clk|fen60:u2|lpm_add_sub:Add1|result_node[1]                                     ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|result_node[2]                                ; |clk|fen60:u2|lpm_add_sub:Add1|result_node[2]                                     ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|result_node[3]                                ; |clk|fen60:u2|lpm_add_sub:Add1|result_node[3]                                     ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]               ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~0                             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~0                                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~3                             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~3                                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~2             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~2                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~3             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~3                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]               ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]               ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]               ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~7                             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~7                                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~8                             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~8                                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~9                             ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~9                                  ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~10                            ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~10                                 ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~11                            ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~11                                 ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~12                            ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~12                                 ; out0             ;
; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~13                            ; |clk|fen60:u2|lpm_add_sub:Add1|addcore:adder|_~13                                 ; out0             ;