hmb_max.tan.rpt

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM2210F324C3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; HC_VGA_CLOCK    ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; HC_NCLK         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; HC_ID_I2CSCL    ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; OSC100          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'HC_VGA_CLOCK'                                                                                                                                                                                                                                      ;
+-------+------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                      ; To                                        ; From Clock   ; To Clock     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 273.15 MHz ( period = 3.661 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[5]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.218 ns                ;
; N/A   ; 273.15 MHz ( period = 3.661 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[7]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.218 ns                ;
; N/A   ; 273.15 MHz ( period = 3.661 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[9]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.218 ns                ;
; N/A   ; 274.35 MHz ( period = 3.645 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[2]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.202 ns                ;
; N/A   ; 274.35 MHz ( period = 3.645 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[3]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.202 ns                ;
; N/A   ; 274.35 MHz ( period = 3.645 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[2]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.202 ns                ;
; N/A   ; 274.35 MHz ( period = 3.645 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[3]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.202 ns                ;
; N/A   ; 289.77 MHz ( period = 3.451 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_B[5]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.008 ns                ;
; N/A   ; 289.77 MHz ( period = 3.451 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_B[7]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.008 ns                ;
; N/A   ; 289.77 MHz ( period = 3.451 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_B[9]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 3.008 ns                ;
; N/A   ; 291.12 MHz ( period = 3.435 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_G[2]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.992 ns                ;
; N/A   ; 291.12 MHz ( period = 3.435 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_G[3]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.992 ns                ;
; N/A   ; 291.12 MHz ( period = 3.435 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_B[2]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.992 ns                ;
; N/A   ; 291.12 MHz ( period = 3.435 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[0] ; VGA_DATA_DECODE:u1|VGA_B[3]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.992 ns                ;
; N/A   ; 298.69 MHz ( period = 3.348 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_R[6]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.905 ns                ;
; N/A   ; 298.69 MHz ( period = 3.348 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_R[7]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.905 ns                ;
; N/A   ; 298.69 MHz ( period = 3.348 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[6]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.905 ns                ;
; N/A   ; 298.69 MHz ( period = 3.348 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[7]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.905 ns                ;
; N/A   ; 298.69 MHz ( period = 3.348 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[6]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.905 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[0]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.730 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_G[1]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.730 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[0]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.730 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[1]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.730 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_R[8]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.727 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_R[9]               ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; None                        ; None                      ; 2.727 ns                ;