hmb_max.tan.rpt

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

Classic Timing Analyzer report for HMB_MAX
Sat Jun 30 13:49:19 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'HC_VGA_CLOCK'
  6. Clock Setup: 'HC_NCLK'
  7. Clock Setup: 'HC_ID_I2CSCL'
  8. Clock Setup: 'OSC100'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Timing Analyzer INI Usage
 14. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                        ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------+-------------------------------+--------------+--------------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                      ; To                            ; From Clock   ; To Clock     ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------+-------------------------------+--------------+--------------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 1.446 ns                                       ; HC_VGA_DATA[2]                            ; VGA_DATA_DECODE:u1|d1_RGB[2]  ; --           ; HC_VGA_CLOCK ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 10.585 ns                                      ; Terasic_I2CBir_bus:u2|cnt[7]              ; HC_ID_I2CDAT                  ; HC_ID_I2CSCL ; --           ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 6.238 ns                                       ; HC_ADC_DIN                                ; ADC_DIN                       ; --           ; --           ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.373 ns                                       ; HC_ID_I2CDAT                              ; Terasic_I2CBir_bus:u2|pre_w_r ; --           ; HC_ID_I2CSCL ; 0            ;
; Clock Setup: 'HC_ID_I2CSCL'  ; N/A   ; None          ; 227.22 MHz ( period = 4.401 ns )               ; Terasic_I2CBir_bus:u2|cnt[3]              ; Terasic_I2CBir_bus:u2|cnt[7]  ; HC_ID_I2CSCL ; HC_ID_I2CSCL ; 0            ;
; Clock Setup: 'HC_VGA_CLOCK'  ; N/A   ; None          ; 273.15 MHz ( period = 3.661 ns )               ; VGA_DATA_DECODE:u1|color_phase_counter[1] ; VGA_DATA_DECODE:u1|VGA_B[9]   ; HC_VGA_CLOCK ; HC_VGA_CLOCK ; 0            ;
; Clock Setup: 'HC_NCLK'       ; N/A   ; None          ; 302.30 MHz ( period = 3.308 ns )               ; LCD_DATA_DECODE:u3|color_phase_counter[0] ; LCD_DATA_DECODE:u3|LCD_B[5]   ; HC_NCLK      ; HC_NCLK      ; 0            ;
; Clock Setup: 'OSC100'        ; N/A   ; None          ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; SAMPLE_CLK[0]                             ; SAMPLE_CLK[5]                 ; OSC100       ; OSC100       ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                           ;                               ;              ;              ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------------------------------+-------------------------------+--------------+--------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+