hmb_max.map.rpt

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

;     -- register cascade mode                ; 0            ;
;     -- synchronous clear/load mode          ; 8            ;
;     -- asynchronous clear/load mode         ; 10           ;
;                                             ;              ;
; Total registers                             ; 158          ;
; Total logic cells in carry chains           ; 13           ;
; I/O pins                                    ; 205          ;
; Maximum fan-out node                        ; HC_VGA_CLOCK ;
; Maximum fan-out                             ; 75           ;
; Total fan-out                               ; 578          ;
; Average fan-out                             ; 1.55         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                             ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name            ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+--------------+
; |HMB_MAX                   ; 169 (7)     ; 158          ; 0          ; 205  ; 0            ; 11 (1)       ; 134 (0)           ; 24 (6)           ; 13 (5)          ; 0 (0)      ; |HMB_MAX                       ; work         ;
;    |LCD_DATA_DECODE:u3|    ; 64 (64)     ; 63           ; 0          ; 0    ; 0            ; 1 (1)        ; 60 (60)           ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |HMB_MAX|LCD_DATA_DECODE:u3    ; work         ;
;    |Terasic_I2CBir_bus:u2| ; 22 (22)     ; 14           ; 0          ; 0    ; 0            ; 8 (8)        ; 2 (2)             ; 12 (12)          ; 8 (8)           ; 0 (0)      ; |HMB_MAX|Terasic_I2CBir_bus:u2 ; work         ;
;    |VGA_DATA_DECODE:u1|    ; 76 (76)     ; 75           ; 0          ; 0    ; 0            ; 1 (1)        ; 72 (72)           ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |HMB_MAX|VGA_DATA_DECODE:u1    ; work         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; SAMPLE_CLK[6..7]                      ; Lost fanout        ;
; Total Number of Removed Registers = 2 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 158   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 10    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 60    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |HMB_MAX|VGA_DATA_DECODE:u1|color_phase_counter[1] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |HMB_MAX|LCD_DATA_DECODE:u3|color_phase_counter[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis INI Usage                                                                                                            ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+
; Option               ; Usage                                                                                                              ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+
; Initialization file: ; c:/altera/71/quartus/bin/quartus.ini                                                                               ;
; dev_password         ; e81f0e65b8afc1da24522b894c886f598ff5e3fafae3453dd1029e508011004342234235215526025211557545361520042000410042555455 ;
+----------------------+--------------------------------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Jun 30 13:49:02 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off HMB_MAX -c HMB_MAX
Info: Found 1 design units, including 1 entities, in source file LCD_DATA_DECODE.v
    Info: Found entity 1: LCD_DATA_DECODE
Info: Found 1 design units, including 1 entities, in source file Terasic_I2CBir_bus.v
    Info: Found entity 1: Terasic_I2CBir_bus
Info: Found 1 design units, including 1 entities, in source file VGA_DATA_DECODE.v
    Info: Found entity 1: VGA_DATA_DECODE
Warning (10238): Verilog Module Declaration warning at HMB_MAX.v(186): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "HMB_MAX"
Warning: Using design file HMB_MAX.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: HMB_MAX
Info: Elaborating entity "HMB_MAX" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at HMB_MAX.v(396): truncated value with size 32 to match size of target (8)
Warning (10034): Output port "HM_SD_DAT" at HMB_MAX.v(218) has no driver
Warning (10034): Output port "VGA_SYNC" at HMB_MAX.v(277) has no driver
Warning (10034): Output port "MD_SD_CMD" at HMB_MAX.v(284) has no driver
Warning (10034): Output port "MD_SD_DAT3" at HMB_MAX.v(285) has no driver
Info: Elaborating entity "VGA_DATA_DECODE" for hierarchy "VGA_DATA_DECODE:u1"
Warning (10230): Verilog HDL assignment warning at VGA_DATA_DECODE.v(244): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "Terasic_I2CBir_bus" for hierarchy "Terasic_I2CBir_bus:u2"
Warning (10230): Verilog HDL assignment warning at Terasic_I2CBir_bus.v(122): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at Terasic_I2CBir_bus.v(148): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at Terasic_I2CBir_bus.v(155): truncated value with size 32 to match size of target (1)
Warning (10034): Output port "ack" at Terasic_I2CBir_bus.v(59) has no driver
Info: Elaborating entity "LCD_DATA_DECODE" for hierarchy "LCD_DATA_DECODE:u3"
Warning (10230): Verilog HDL assignment warning at LCD_DATA_DECODE.v(316): truncated value with size 32 to match size of target (2)
Warning: The bidir "MD_I2C_SDAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "MD_PS2_CLK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "MD_PS2_DAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "MD_MDIO" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "MD_SDA" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "HM_I2C_SDAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "HM_PS2_CLK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "HM_PS2_DAT" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "HM_MDIO" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "HM_SDA" has no source; inserted an always disabled tri-state buffer.
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "VGA_SYNC" stuck at GND
    Warning: Pin "MD_SD_CMD" stuck at GND
    Warning: Pin "MD_SD_DAT3" stuck at GND
    Warning: Pin "HM_SD_DAT" stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "SAMPLE_CLK[6]" lost all its fanouts during netlist optimizations.
    Info: Register "SAMPLE_CLK[7]" lost all its fanouts during netlist optimizations.
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "MD_SD_DAT"
    Warning: No output dependent on input pin "HC_VGA_SYNC"
    Warning: No output dependent on input pin "HM_SD_CMD"
    Warning: No output dependent on input pin "HM_SD_DAT3"
Info: Implemented 374 device resources after synthesis - the final resource count might be different
    Info: Implemented 79 input pins
    Info: Implemented 114 output pins
    Info: Implemented 12 bidirectional pins
    Info: Implemented 169 logic cells
Info: Generated suppressed messages file D:/code/HMB V1.1/MAX code/final/2007.6.29/HMB_MAX code V1.1/HMB_MAX.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Sat Jun 30 13:49:05 2007
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/code/HMB V1.1/MAX code/final/2007.6.29/HMB_MAX code V1.1/HMB_MAX.map.smsg.