hmb_max.fit.eqn

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

D1_oLCD_RGB_Delay[7]_lut_out = HC_LCD_DATA[7];
D1_oLCD_RGB_Delay[7] = DFFEAS(D1_oLCD_RGB_Delay[7]_lut_out, GLOBAL(HC_NCLK), VCC, , , , , , );


--D1_LCD_HD_Delay[3] is LCD_DATA_DECODE:u3|LCD_HD_Delay[3] at LC_X15_Y11_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_HD_Delay[3]_lut_out = GND;
D1_LCD_HD_Delay[3] = DFFEAS(D1_LCD_HD_Delay[3]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_HD_Delay[2], , , VCC);


--D1_LCD_VD_Delay[3] is LCD_DATA_DECODE:u3|LCD_VD_Delay[3] at LC_X12_Y11_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_VD_Delay[3]_lut_out = GND;
D1_LCD_VD_Delay[3] = DFFEAS(D1_LCD_VD_Delay[3]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_VD_Delay[2], , , VCC);


--D1_LCD_DEN_Delay[3] is LCD_DATA_DECODE:u3|LCD_DEN_Delay[3] at LC_X15_Y12_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_DEN_Delay[3]_lut_out = GND;
D1_LCD_DEN_Delay[3] = DFFEAS(D1_LCD_DEN_Delay[3]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_DEN_Delay[2], , , VCC);


--C1L37Q is Terasic_I2CBir_bus:u2|w_r~reg0 at LC_X9_Y9_N0
--operation mode is normal

C1L37Q_lut_out = C1L3 & C1_pre_w_r & (!A1L52) # !C1L3 & (C1L37Q);
C1L37Q = DFFEAS(C1L37Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , , , , );


--C1L9Q is Terasic_I2CBir_bus:u2|cnt[0]~reg0 at LC_X8_Y9_N0
--operation mode is arithmetic

C1L9Q_lut_out = !C1L9Q;
C1L9Q = DFFEAS(C1L9Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , VCC, , , C1L6);

--C1L7 is Terasic_I2CBir_bus:u2|cnt[0]~119 at LC_X8_Y9_N0
--operation mode is arithmetic

C1L7_cout_0 = C1L9Q;
C1L7 = CARRY(C1L7_cout_0);

--C1L8 is Terasic_I2CBir_bus:u2|cnt[0]~119COUT1_157 at LC_X8_Y9_N0
--operation mode is arithmetic

C1L8_cout_1 = C1L9Q;
C1L8 = CARRY(C1L8_cout_1);


--C1L18Q is Terasic_I2CBir_bus:u2|cnt[3]~reg0 at LC_X8_Y9_N3
--operation mode is arithmetic

C1L18Q_lut_out = C1L18Q $ (C1L13);
C1L18Q = DFFEAS(C1L18Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , VCC, , , C1L6);

--C1L16 is Terasic_I2CBir_bus:u2|cnt[3]~123 at LC_X8_Y9_N3
--operation mode is arithmetic

C1L16_cout_0 = !C1L13 # !C1L18Q;
C1L16 = CARRY(C1L16_cout_0);

--C1L17 is Terasic_I2CBir_bus:u2|cnt[3]~123COUT1_162 at LC_X8_Y9_N3
--operation mode is arithmetic

C1L17_cout_1 = !C1L14 # !C1L18Q;
C1L17 = CARRY(C1L17_cout_1);


--C1L25Q is Terasic_I2CBir_bus:u2|cnt[5]~reg0 at LC_X8_Y9_N5
--operation mode is arithmetic

C1L25Q_carry_eqn = (!C1L19 & GND) # (C1L19 & VCC);
C1L25Q_lut_out = C1L25Q $ (C1L25Q_carry_eqn);
C1L25Q = DFFEAS(C1L25Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);

--C1L23 is Terasic_I2CBir_bus:u2|cnt[5]~127 at LC_X8_Y9_N5
--operation mode is arithmetic

C1L23_cout_0 = !C1L19 # !C1L25Q;
C1L23 = CARRY(C1L23_cout_0);

--C1L24 is Terasic_I2CBir_bus:u2|cnt[5]~127COUT1_164 at LC_X8_Y9_N5
--operation mode is arithmetic

C1L24_cout_1 = !C1L19 # !C1L25Q;
C1L24 = CARRY(C1L24_cout_1);


--C1L28Q is Terasic_I2CBir_bus:u2|cnt[6]~reg0 at LC_X8_Y9_N6
--operation mode is arithmetic

C1L28Q_carry_eqn = (!C1L19 & C1L23) # (C1L19 & C1L24);
C1L28Q_lut_out = C1L28Q $ (!C1L28Q_carry_eqn);
C1L28Q = DFFEAS(C1L28Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);

--C1L26 is Terasic_I2CBir_bus:u2|cnt[6]~131 at LC_X8_Y9_N6
--operation mode is arithmetic

C1L26_cout_0 = C1L28Q & (!C1L23);
C1L26 = CARRY(C1L26_cout_0);

--C1L27 is Terasic_I2CBir_bus:u2|cnt[6]~131COUT1_166 at LC_X8_Y9_N6
--operation mode is arithmetic

C1L27_cout_1 = C1L28Q & (!C1L24);
C1L27 = CARRY(C1L27_cout_1);


--C1L29Q is Terasic_I2CBir_bus:u2|cnt[7]~reg0 at LC_X8_Y9_N7
--operation mode is normal

C1L29Q_carry_eqn = (!C1L19 & C1L26) # (C1L19 & C1L27);
C1L29Q_lut_out = C1L29Q $ C1L29Q_carry_eqn;
C1L29Q = DFFEAS(C1L29Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);


--C1L1 is Terasic_I2CBir_bus:u2|Equal~165 at LC_X8_Y9_N9
--operation mode is normal

C1L1 = !C1L28Q & !C1L29Q & !C1L25Q & C1L18Q;


--C1L12Q is Terasic_I2CBir_bus:u2|cnt[1]~reg0 at LC_X8_Y9_N1
--operation mode is arithmetic

C1L12Q_lut_out = C1L12Q $ C1L7;
C1L12Q = DFFEAS(C1L12Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);

--C1L10 is Terasic_I2CBir_bus:u2|cnt[1]~139 at LC_X8_Y9_N1
--operation mode is arithmetic

C1L10_cout_0 = !C1L7 # !C1L12Q;
C1L10 = CARRY(C1L10_cout_0);

--C1L11 is Terasic_I2CBir_bus:u2|cnt[1]~139COUT1_159 at LC_X8_Y9_N1
--operation mode is arithmetic

C1L11_cout_1 = !C1L8 # !C1L12Q;
C1L11 = CARRY(C1L11_cout_1);


--C1L15Q is Terasic_I2CBir_bus:u2|cnt[2]~reg0 at LC_X8_Y9_N2
--operation mode is arithmetic

C1L15Q_lut_out = C1L15Q $ !C1L10;
C1L15Q = DFFEAS(C1L15Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);

--C1L13 is Terasic_I2CBir_bus:u2|cnt[2]~143 at LC_X8_Y9_N2
--operation mode is arithmetic

C1L13_cout_0 = C1L15Q & !C1L10;
C1L13 = CARRY(C1L13_cout_0);

--C1L14 is Terasic_I2CBir_bus:u2|cnt[2]~143COUT1_161 at LC_X8_Y9_N2
--operation mode is arithmetic

C1L14_cout_1 = C1L15Q & !C1L11;
C1L14 = CARRY(C1L14_cout_1);


--C1L2 is Terasic_I2CBir_bus:u2|Equal~166 at LC_X9_Y9_N6
--operation mode is normal

C1L2 = !C1L12Q & !C1L15Q;


--C1L22Q is Terasic_I2CBir_bus:u2|cnt[4]~reg0 at LC_X8_Y9_N4
--operation mode is arithmetic

C1L22Q_lut_out = C1L22Q $ (!C1L16);
C1L22Q = DFFEAS(C1L22Q_lut_out, !HC_ID_I2CSCL, !C1_tr, , , ~GND, , , C1L6);

--C1L19 is Terasic_I2CBir_bus:u2|cnt[4]~147 at LC_X8_Y9_N4
--operation mode is arithmetic

C1L19 = C1L20;


--C1L3 is Terasic_I2CBir_bus:u2|Equal~167 at LC_X9_Y9_N8
--operation mode is normal

C1L3 = C1L9Q & !C1L22Q & C1L1 & C1L2;


--C1L30 is Terasic_I2CBir_bus:u2|i2c_rw~33 at LC_X9_Y9_N9
--operation mode is normal

C1L30 = C1L37Q $ C1L3;


--B1_v_cnt[0] is vga_mode3_decode:u1|v_cnt[0] at LC_X16_Y3_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_v_cnt[0]_lut_out = GND;
B1_v_cnt[0] = DFFEAS(B1_v_cnt[0]_lut_out, !GLOBAL(HC_VGA_CLOCK), !HC_VGA_VS, , B1L9, B1L79, , , VCC);


--D1_LCD_HD_Delay[2] is LCD_DATA_DECODE:u3|LCD_HD_Delay[2] at LC_X15_Y11_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_HD_Delay[2]_lut_out = GND;
D1_LCD_HD_Delay[2] = DFFEAS(D1_LCD_HD_Delay[2]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_HD_Delay[1], , , VCC);


--D1_LCD_VD_Delay[2] is LCD_DATA_DECODE:u3|LCD_VD_Delay[2] at LC_X12_Y11_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_VD_Delay[2]_lut_out = GND;
D1_LCD_VD_Delay[2] = DFFEAS(D1_LCD_VD_Delay[2]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_VD_Delay[1], , , VCC);


--D1_LCD_DEN_Delay[2] is LCD_DATA_DECODE:u3|LCD_DEN_Delay[2] at LC_X15_Y12_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_DEN_Delay[2]_lut_out = GND;
D1_LCD_DEN_Delay[2] = DFFEAS(D1_LCD_DEN_Delay[2]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_DEN_Delay[1], , , VCC);


--C1_pre_w_r is Terasic_I2CBir_bus:u2|pre_w_r at LC_X9_Y9_N5
--operation mode is normal

C1_pre_w_r_lut_out = C1L4 & (A1L52) # !C1L4 & C1_pre_w_r;
C1_pre_w_r = DFFEAS(C1_pre_w_r_lut_out, !HC_ID_I2CSCL, !C1_tr, , , , , , );


--C1L35Q is Terasic_I2CBir_bus:u2|rx_stop~reg0 at LC_X10_Y9_N7
--operation mode is normal

C1L35Q_lut_out = !C1_prev_sda & C1_prev_scl & A1L52 & HC_ID_I2CSCL;
C1L35Q = DFFEAS(C1L35Q_lut_out, SAMPLE_CLK[5], VCC, , , , , , );


--C1L34Q is Terasic_I2CBir_bus:u2|rx_start~reg0 at LC_X10_Y9_N9
--operation mode is normal

C1L34Q_lut_out = C1_prev_sda & C1_prev_scl & !A1L52 & HC_ID_I2CSCL;
C1L34Q = DFFEAS(C1L34Q_lut_out, SAMPLE_CLK[5], VCC, , , , , , );


--C1_tr is Terasic_I2CBir_bus:u2|tr at LC_X9_Y9_N4
--operation mode is normal

C1_tr = C1L34Q # C1L35Q;


--C1L5 is Terasic_I2CBir_bus:u2|LessThan~120 at LC_X9_Y9_N7
--operation mode is normal

C1L5 = C1L22Q & (C1L9Q # C1L18Q # !C1L2);


--C1L6 is Terasic_I2CBir_bus:u2|LessThan~121 at LC_X8_Y9_N8
--operation mode is normal

C1L6 = C1L25Q # C1L29Q # C1L28Q # C1L5;


--D1_LCD_HD_Delay[1] is LCD_DATA_DECODE:u3|LCD_HD_Delay[1] at LC_X16_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_HD_Delay[1]_lut_out = GND;
D1_LCD_HD_Delay[1] = DFFEAS(D1_LCD_HD_Delay[1]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_HD_Delay[0], , , VCC);


--D1_LCD_VD_Delay[1] is LCD_DATA_DECODE:u3|LCD_VD_Delay[1] at LC_X12_Y11_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_VD_Delay[1]_lut_out = GND;
D1_LCD_VD_Delay[1] = DFFEAS(D1_LCD_VD_Delay[1]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_VD_Delay[0], , , VCC);


--D1_LCD_DEN_Delay[1] is LCD_DATA_DECODE:u3|LCD_DEN_Delay[1] at LC_X15_Y12_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_LCD_DEN_Delay[1]_lut_out = GND;
D1_LCD_DEN_Delay[1] = DFFEAS(D1_LCD_DEN_Delay[1]_lut_out, GLOBAL(HC_NCLK), VCC, , , D1_LCD_DEN_Delay[0], , , VCC);


--C1L4 is Terasic_I2CBir_bus:u2|Equal~168 at LC_X9_Y9_N1
--operation mode is normal

C1L4 = !C1L9Q & C1L2 & C1L1 & !C1L22Q;


--C1_prev_scl is Terasic_I2CBir_bus:u2|prev_scl at LC_X10_Y9_N0
--operation mode is normal

C1_prev_scl_lut_out = HC_ID_I2CSCL;
C1_prev_scl = DFFEAS(C1_prev_scl_lut_out, SAMPLE_CLK[5], VCC, , , , , , );


--C1_prev_sda is Terasic_I2CBir_bus:u2|prev_sda at LC_X10_Y9_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C1_prev_sda_lut_out = GND;
C1_prev_sda = DFFEAS(C1_prev_sda_lut_out, SAMPLE_CLK[5], VCC, , , A1L52, , , VCC);


--SAMPLE_CLK[5] is SAMPLE_CLK[5] at LC_X10_Y9_N6
--operation mode is normal

SAMPLE_CLK[5]_carry_eqn = (!A1L170 & A1L174) # (A1L170 & A1L175);
SAMPLE_CLK[5]_lut_out = SAMPLE_CLK[5] $ (SAMPLE_CLK[5]_carry_eqn);
SAMPLE_CLK[5] = DFFEAS(SAMPLE_CLK[5]_lut_out, GLOBAL(OSC100), VCC, , , , , , );


--D1_LCD_HD_Delay[0] is LCD_DATA_DECODE:u3|LCD_HD_Delay[0] at LC_X16_Y11_N4
--operation mode is normal

D1_LCD_HD_Delay[0]_lut_out = HC_HD;
D1_LCD_HD_Delay[0] = DFFEAS(D1_LCD_HD_Delay[0]_lut_out, GLOBAL(HC_NCLK), VCC, , , , , , );


--D1_LCD_DEN_Delay[0] is LCD_DATA_DECODE:u3|LCD_DEN_Delay[0] at LC_X15_Y12_N7
--operation mode is normal

D1_LCD_DEN_Delay[0]_lut_out = HC_DEN;
D1_LCD_DEN_Delay[0] = DFFEAS(D1_LCD_DEN_Delay[0]_lut_out, GLOBAL(HC_NCLK), VCC, , , , , , );


--SAMPLE_CLK[4] is SAMPLE_CLK[4] at LC_X10_Y9_N5
--operation mode is arithmetic

SAMPLE_CLK[4]_carry_eqn = (!A1L170 & GND) # (A1L170 & VCC);
SAMPLE_CLK[4]_lut_out = SAMPLE_CLK[4] $ (!SAMPLE_CLK[4]_carry_eqn);
SAMPLE_CLK[4] = DFFEAS(SAMPLE_CLK[4]_lut_out, GLOB