lcd_data_decode.v

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

////////////////////////////////////////////////////////////////
//
// LCD_DATA_DECODE
//
//
// OVERVIEW
//   This core is a simple 8 -> 24 data-demultiplexer, which is the
//   final logic driving the Toppoly TD043MTEA LCD display panel.
//   The display-panel input expects one pixel per clock at 33.3MHz,
//   where each pixel is 24 bits of data (8B + 8G + 8R), presented in
//   parallel.
//
//   This logic resides in a MAX device which sits on a daughtercard
//   next to the panel and presents a reduced-pincount interface to
//   the FPGA, like this:
//
//   ~~----------------------+   +-----------------------------------------+
//   ..                      |   |                                         |
//   ..    +--------+        |   |        +------+        +--------------+ |
//   ..    |        |        [[H]]        |      |---/--->| R            | |
//   ..    |  FPGA  | B,G,R  [[S]] B,G,R  | MAX  |   8    |              | |
//   ..    |        |----/-->[[M]]---/--->|(incl |---/--->| G   LCD      | |
//   ..    |        |    8   [[C]]   8    | This |   8    |    Display   | |
//   ..    +--------+        |   |        | Core)|---/--->| B            | |
//   ..                      |   |        +------+   8    +--------------+ |
//   ..                      |   |                                         |
//   ..    Host Board        |   |     Daughtercard                        |
//   ~~----------------------+   +-----------------------------------------+
//
//
//   Of course, the 8-bit data comes in at 3x the rate (100MHz) of the
//   24-bit samples we drive to the display.  The 8-bit data is also
//   accompanied by the display's sync-signals:
//
//          HD:     Horizontal (line) sync-pulse
//          VD:     Vertical (frame) sync-pulse
//          DEN:    Data-qualification
//
// PRINCIPLES of OPERATION
//
//   All of the BGR-data and sync-signals coming from the FPGA are
//   immediately captured in registers.  The FPGA provides the
//   fundamental capture-clock (inexplicably-named "MUTI_clk",
//   but which I rename to "clk" for the purposes of simplicity and clarity)
//   at 3x the picture-rate. All input- and output-signals are
//   referenced to the rising edge of clk.
//
// SYNC-SIGNAL TIMING (input and output)
//
//   This logic delays the incoming VD, HD, and DEN all by the same
//   fixed number of clock-cycles (which doesn't matter), and presents
//   them, otherwise-unmodified, to the LCD panel.
//
//       (the net-delay for R happens to be four clock-cycles, but
//       that number is implementation-dependent).
//
// INPUT-DATA TIMING
//
//   The 8-bit-wide HC_LCD_DATA signal is presumed to contain a stream
//   of color pixel data, with each pixel represented by three
//   successive clock-cycles of the stream.  The data is presented as
//   "BGR," in that order.
//
//   This circuit uses the HD pulse to determine the position of the
//   BLUE color-sample, and thus the start of each three-clock
//   pixel-period.  State-transitions on HD (0-->1 or 1-->0) coincide
//   with the presentation of BLUE color on the HC_LCD_DATA input.  The
//   GREEN and RED values for that same pixel are presented on the
//   next two clock-cycles.
//
//                         INPUT-DATA TIMING
//               Color-phase referened to HD-transitions.
//       
//          
//            ___       ___       ___       ___       ___       __ 
//  clk      /   \     /   \     /   \     /   \     /   \     /       
//         _/     \___/     \___/     \___/     \___/     \___/
//         
//               _______   _______   _______   _______   _______         
//            \ /       \ /       \ /       \ /       \ /       \ /
//  RGB-in     x    B    x    G    x    R    x    B    x    G    x 
//            / \_______/ \_______/ \_______/ \_______/ \_______/ \
//               
//               
//       _____                                _____________________ 
//            \                              /     
//  HD         \                            /     
//              \__________________________/     
//
//
//   HD is not allowed to change state except at pixel-boundaries.
//   Again: This circuit uses state-transitions on the HD-signal to
//   synchronize its internal counters.
//
//
// OUTPUT TIMING
//
//   This circuit generates an outgoing clock (NCLK) to the LCD
//   panel.  This clock runs at 1/3 the frequency of the incoming clk.
//
//  
//            ___       ___       ___       ___       ___       __ 
//  clk      /   \     /   \     /   \     /   \     /   \     /       
//         _/     \___/     \___/     \___/     \___/     \___/  
//                                     
//               ___________________________   ____________________         
//            \ /                           \ /                  
//  LCD data   x           {R:G:B}           x           {R:G:B}  
//            / \___________________________/ \____________________
//
//                                          
//               ___________________________   ____________________         
// LCD_...    \ /                           \ /  
// Sync        x          HD,VD,DEN          x          HD,VD,DEN
// Signals    / \___________________________/ \____________________
//
//
//         _____________             _________________             __    
//                      \           /                 \           /  
//    NCLK               \         /                   \         /   
//                        \_______/                     \_______/    
//                      
//           
// Notice that NCLK transitions on different edges of clk than the RGB
// Data and sync-signals.  This has the favorable effect that the
// sync- and data-signals to the LCD are stable on *both* the falling
// *and* rising edges of NCLK...so the LCD-panel can capture these signals
// on either edge at no penalty.
//
// This is one of the advantages of generating slow timing waveforms
// off of a faster clock:  You can place the signal-edges anywhere you
// like, with very-well-defined timing-relationships to each other,
// limited only by the granularity of the faster clock.
//
// Any time you find yourself generating timing waveforms, ask
// yourself:  "would my life be simpler if I used a much-faster clock
// to help me place the edges exactly where I want them?"  The answer
// is always "Yes, of course my life would be simpler."  The only
// reason to *not* do this is the inability to use or generate a
// faster cloock.  In this case:  We have a faster clock already
// lying-around, so we'd be nuts to *not* use it.
//

module LCD_DATA_DECODE
  (
   clk,
   reset_n,
   
   RGB_in,
   HD_in,
   VD_in,
   DEN_in,
   
   LCD_R,
   LCD_G,
   LCD_B,
   LCD_HD,
   LCD_VD,
   LCD_DEN,
   LCD_NCLK
   );
   

   input        clk;
   input        reset_n;
   
   input [7:0]  RGB_in;
   input        HD_in;
   input        VD_in;
   input        DEN_in;

   output [7:0] LCD_R;
   output [7:0] LCD_G;
   output [7:0] LCD_B;
   output 	LCD_HD;
   output 	LCD_VD;
   output 	LCD_DEN;
   output 	LCD_NCLK;

   ////////////////
   // Input-capture & delay.
   //
   //   First: Capture all the inputs into registers.  Doing anything
   //   else would be nuts!  We *swear* to never use the raw versions
   //   of these signals right from the input-pins.  Using those
   //   signals would be nuts!
   //
   //   Also, while we're here clocking input-data values into
   //   registers, it's easy to build a delay-line.  We (obviously)
   //   need to do this for the data, because we need three past
   //   values in our hands to compose the 24-bit output.  And:
   //   Because the sync-signals have to be, um, SYNCHRONIZED with the
   //   data, we have to delay them exactly as many times as we delay
   //   the data.  So the incoming signals are not only captured,
   //   they're also delayed two additional clock-cycles for
   //   coherent presentation on the ouptut.
   //
   //   Note: I could implement the sync-signal delay-chains
   //   multi-bit-wide registers and the Verilog shift-operator.  But
   //   there's nothing like three explicitly-named signals for
   //   explicitness.
   //
   reg [7:0] d1_RGB;
   reg [7:0] d2_RGB;