hmb_max.fit.rpt

ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daugh

+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EPM2210F324C3                  ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/code/HMB V1.1/MAX code/final/2007.6.29/HMB_MAX code V1.1/HMB_MAX.pin.


+----------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                              ;
+---------------------------------------------+------------------------------+
; Resource                                    ; Usage                        ;
+---------------------------------------------+------------------------------+
; Total logic elements                        ; 169 / 2,210 ( 8 % )          ;
;     -- Combinational with no register       ; 11                           ;
;     -- Register only                        ; 134                          ;
;     -- Combinational with a register        ; 24                           ;
;                                             ;                              ;
; Logic element usage by number of LUT inputs ;                              ;
;     -- 4 input functions                    ; 10                           ;
;     -- 3 input functions                    ; 2                            ;
;     -- 2 input functions                    ; 20                           ;
;     -- 1 input functions                    ; 67                           ;
;     -- 0 input functions                    ; 70                           ;
;                                             ;                              ;
; Logic elements by mode                      ;                              ;
;     -- normal mode                          ; 158                          ;
;     -- arithmetic mode                      ; 11                           ;
;     -- qfbk mode                            ; 0                            ;
;     -- register cascade mode                ; 0                            ;
;     -- synchronous clear/load mode          ; 77                           ;
;     -- asynchronous clear/load mode         ; 10                           ;
;                                             ;                              ;
; Total registers                             ; 158 / 2,210 ( 7 % )          ;
; Total LABs                                  ; 23 / 221 ( 10 % )            ;
; Logic elements in carry chains              ; 13                           ;
; User inserted logic elements                ; 0                            ;