📄 qwe.tan.rpt
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Timing Analyzer report for qwe
Thu Apr 23 11:13:24 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.142 ns ; g2 ; Q0[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C20F484C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-------+-------+
; N/A ; None ; 13.142 ns ; g2 ; Q0[7] ;
; N/A ; None ; 12.910 ns ; g2 ; Q0[4] ;
; N/A ; None ; 12.831 ns ; g1 ; Q0[7] ;
; N/A ; None ; 12.770 ns ; g2 ; Q0[1] ;
; N/A ; None ; 12.770 ns ; g2 ; Q0[6] ;
; N/A ; None ; 12.761 ns ; g3 ; Q0[7] ;
; N/A ; None ; 12.749 ns ; g2 ; Q0[3] ;
; N/A ; None ; 12.744 ns ; g2 ; Q0[5] ;
; N/A ; None ; 12.739 ns ; g2 ; Q0[2] ;
; N/A ; None ; 12.734 ns ; g2 ; Q0[0] ;
; N/A ; None ; 12.599 ns ; g1 ; Q0[4] ;
; N/A ; None ; 12.593 ns ; Q1[1] ; Q0[7] ;
; N/A ; None ; 12.560 ns ; Q1[1] ; Q0[1] ;
; N/A ; None ; 12.558 ns ; Q1[1] ; Q0[6] ;
; N/A ; None ; 12.553 ns ; Q1[1] ; Q0[4] ;
; N/A ; None ; 12.552 ns ; Q1[1] ; Q0[3] ;
; N/A ; None ; 12.552 ns ; Q1[0] ; Q0[7] ;
; N/A ; None ; 12.533 ns ; Q1[1] ; Q0[2] ;
; N/A ; None ; 12.529 ns ; g3 ; Q0[4] ;
; N/A ; None ; 12.515 ns ; Q1[0] ; Q0[1] ;
; N/A ; None ; 12.513 ns ; Q1[0] ; Q0[3] ;
; N/A ; None ; 12.468 ns ; Q1[0] ; Q0[4] ;
; N/A ; None ; 12.466 ns ; Q1[0] ; Q0[6] ;
; N/A ; None ; 12.459 ns ; g1 ; Q0[1] ;
; N/A ; None ; 12.459 ns ; g1 ; Q0[6] ;
; N/A ; None ; 12.446 ns ; Q1[0] ; Q0[2] ;
; N/A ; None ; 12.438 ns ; g1 ; Q0[3] ;
; N/A ; None ; 12.433 ns ; g1 ; Q0[5] ;
; N/A ; None ; 12.428 ns ; g1 ; Q0[2] ;
; N/A ; None ; 12.423 ns ; g1 ; Q0[0] ;
; N/A ; None ; 12.389 ns ; g3 ; Q0[1] ;
; N/A ; None ; 12.389 ns ; g3 ; Q0[6] ;
; N/A ; None ; 12.368 ns ; g3 ; Q0[3] ;
; N/A ; None ; 12.363 ns ; g3 ; Q0[5] ;
; N/A ; None ; 12.358 ns ; g3 ; Q0[2] ;
; N/A ; None ; 12.353 ns ; g3 ; Q0[0] ;
; N/A ; None ; 12.197 ns ; Q1[1] ; Q0[5] ;
; N/A ; None ; 12.181 ns ; Q1[1] ; Q0[0] ;
; N/A ; None ; 12.153 ns ; Q1[0] ; Q0[5] ;
; N/A ; None ; 12.152 ns ; Q1[2] ; Q0[7] ;
; N/A ; None ; 12.119 ns ; Q1[2] ; Q0[1] ;
; N/A ; None ; 12.119 ns ; Q1[2] ; Q0[4] ;
; N/A ; None ; 12.117 ns ; Q1[2] ; Q0[6] ;
; N/A ; None ; 12.113 ns ; Q1[2] ; Q0[3] ;
; N/A ; None ; 12.097 ns ; Q1[2] ; Q0[2] ;
; N/A ; None ; 12.096 ns ; Q1[0] ; Q0[0] ;
; N/A ; None ; 11.756 ns ; Q1[2] ; Q0[5] ;
; N/A ; None ; 11.747 ns ; Q1[2] ; Q0[0] ;
+-------+-------------------+-----------------+-------+-------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Apr 23 11:13:24 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qwe -c qwe --timing_analysis_only
Info: Longest tpd from source pin "g2" to destination pin "Q0[7]" is 13.142 ns
Info: 1: + IC(0.000 ns) + CELL(0.925 ns) = 0.925 ns; Loc. = PIN_W5; Fanout = 1; PIN Node = 'g2'
Info: 2: + IC(5.982 ns) + CELL(0.499 ns) = 7.406 ns; Loc. = LCCOMB_X3_Y1_N12; Fanout = 8; COMB Node = 'decoder38:inst|process0~15'
Info: 3: + IC(2.428 ns) + CELL(3.308 ns) = 13.142 ns; Loc. = PIN_AA8; Fanout = 0; PIN Node = 'Q0[7]'
Info: Total cell delay = 4.732 ns ( 36.01 % )
Info: Total interconnect delay = 8.410 ns ( 63.99 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Apr 23 11:13:24 2009
Info: Elapsed time: 00:00:01
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