m8.vhd

来自「这是一个8分频的VHDL语言设计程序」· VHDL 代码 · 共 25 行

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m8 is
port(clk_in:in std_logic;
     clk_out:out std_logic);
end m8;
architecture com of m8 is
signal count:std_logic_vector(2 downto 0);
begin
 process(clk_in)
  begin
  if clk_in'event and clk_in='1' then
    if count<"111" then
       count<=count+1;
       clk_out<='0';
    else count<="000";
         clk_out<='1';
    end if;
   end if;
  end process;
end com;